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/linux/Documentation/devicetree/bindings/ata/
H A Dnvidia,tegra-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/nvidia,tegra-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra AHCI SATA Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra124-ahci
17 - nvidia,tegra132-ahci
18 - nvidia,tegra210-ahci
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H A Dsata-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/sata-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Serial AT attachment (SATA) controllers
10 - Linus Walleij <linus.walleij@linaro.org>
14 AT attachment (SATA) storage devices. It doesn't constitute a device tree
18 The SATA controller-specific device tree bindings are responsible for
23 pattern: "^sata(@.*)?$"
25 Specifies the host controller node. SATA host controller nodes are named
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H A Dfsl,pq-sata.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/fsl,pq-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale 8xxx/3.0 Gb/s SATA nodes
10 - J. Neuschäfer <j.ne@posteo.net>
13 SATA nodes are defined to describe on-chip Serial ATA controllers.
14 Each SATA controller should have its own node.
19 - items:
20 - enum:
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H A Drenesas,rcar-sata.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Serial-ATA Interface
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - items:
16 - enum:
17 - renesas,sata-r8a7779 # R-Car H1
18 - items:
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H A Dcortina,gemini-sata-bridge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cortina Systems Gemini SATA Bridge
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
15 them in different configurations to two SATA ports.
19 const: cortina,gemini-sata-bridge
26 description: phandles to the reset lines for both SATA bridges
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H A Dimx-sata.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/imx-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX AHCI SATA Controller
10 - Shawn Guo <shawn.guo@linaro.org>
13 The Freescale i.MX SATA controller mostly conforms to the AHCI interface
19 - fsl,imx53-ahci
20 - fsl,imx6q-ahci
21 - fsl,imx6qp-ahci
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H A Dahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
14 This document defines device tree properties for a common AHCI SATA
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
24 - $ref: sata-common.yaml#
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H A Dbaikal,bt1-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 SoC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
14 DWC AHCI SATA v4.10a IP-core.
17 - $ref: snps,dwc-ahci-common.yaml#
21 const: baikal,bt1-ahci
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H A Dsnps,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller.
20 - snps,dwc-ahci
21 - snps,spear-ahci
23 - compatible
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H A Dfaraday,ftide010.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
15 platform. The controller can do PIO modes 0 through 4, Multi-word DMA
16 (MWDM) modes 0 through 2 and Ultra DMA modes 0 through 6.
19 SATA bridge in order to support SATA. This is why a phandle to that
22 The timing properties are unique per-SoC, not per-board.
27 - const: faraday,ftide010
28 - items:
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H A Dbrcm,sata-brcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
11 Each SATA controller should have its own node.
14 - Florian Fainelli <f.fainelli@gmail.com>
17 - $ref: ahci-common.yaml#
22 - items:
23 - enum:
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/linux/Documentation/devicetree/bindings/phy/
H A Dbrcm,sata-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <f.fainelli@gmail.com>
14 pattern: "^sata[-|_]phy(@.*)?$"
18 - items:
19 - enum:
20 - brcm,bcm7216-sata-phy
21 - brcm,bcm7425-sata-phy
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H A Dphy-miphy365x.txt5 for SATA and PCIe.
8 - compatible : Should be "st,miphy365x-phy"
9 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
11 an entry for each port sub-node, specifying the control
14 Required nodes : A sub-node is required for each channel the controller
16 'reg' and 'reg-names' properties are used inside these
21 - #phy-cells : Should be 1 (See second example)
23 - PHY_TYPE_SATA
24 - PHY_TYPE_PCI
25 - reg : Address and length of register sets for each device in
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H A Dmarvell,berlin2-sata-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/marvell,berlin2-sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Berlin SATA PHY
10 - Antoine Tenart <atenart@kernel.org>
15 - marvell,berlin2-sata-phy
16 - marvell,berlin2q-sata-phy
24 '#address-cells':
27 '#size-cells':
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H A Dqcom,sata-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SATA PHY Controller
10 - Bjorn Andersson <andersson@kernel.org>
11 - Konrad Dybcio <konrad.dybcio@linaro.org>
14 The Qualcomm SATA PHY describes on-chip SATA Physical layer controllers.
19 - qcom,ipq806x-sata-phy
20 - qcom,apq8064-sata-phy
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H A Dmarvell,mvebu-sata-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/marvell,mvebu-sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell MVEBU SATA PHY
10 - Andrew Lunn <andrew@lunn.ch>
11 - Gregory Clement <gregory.clement@bootlin.com>
15 const: marvell,mvebu-sata-phy
23 clock-names:
25 - const: sata
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H A Dhisilicon,hix5hd2-sata-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/hisilicon,hix5hd2-sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon hix5hd2 SATA PHY
10 - Jiancheng Xue <xuejiancheng@huawei.com>
14 const: hisilicon,hix5hd2-sata-phy
19 '#phy-cells':
20 const: 0
22 hisilicon,peripheral-syscon:
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H A Dphy-miphy28lp.txt5 for SATA, PCIe or USB3.
8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
10 which contain the SATA, PCIe or USB3 mode setting bits.
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
19 - #phy-cells : Should be 1 (See second example)
21 - PHY_TYPE_SATA
22 - PHY_TYPE_PCI
23 - PHY_TYPE_USB3
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/linux/drivers/phy/st/
H A Dphy-spear1340-miphy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ST spear1340-miphy driver
12 #include <linux/dma-mapping.h>
23 #define SPEAR1340_PCM_CFG 0x100
25 #define SPEAR1340_PCM_WKUP_CFG 0x104
26 #define SPEAR1340_SWITCH_CTR 0x108
28 #define SPEAR1340_PERIP1_SW_RST 0x318
30 #define SPEAR1340_PERIP2_SW_RST 0x31C
31 #define SPEAR1340_PERIP3_SW_RST 0x320
33 /* PCIE - SATA configuration registers */
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/linux/drivers/ata/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 # SATA/PATA driver configuration
10 uses pata-platform driver to enable the relevant driver in the
21 If you want to use an ATA hard disk, ATA tape drive, ATA CD-ROM or
62 <file:Documentation/admin-guide/kernel-parameters.txt>.
76 This option adds support for ATA-related ACPI objects.
85 bool "SATA Zero Power Optical Disc Drive (ZPODD) support"
88 This option adds support for SATA Zero Power Optical Disc
98 bool "SATA Port Multiplier support"
102 This option adds support for SATA Port Multipliers
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H A Dsata_gemini.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cortina Systems Gemini SATA bridge add-on to Faraday FTIDE010
23 * struct sata_gemini - a state container for a Gemini SATA bridge
28 * @sata_bridge: if the device enables the SATA bridge
43 #define GEMINI_GLOBAL_MISC_CTRL 0x30
47 * Bits 26:24 are "IDE IO Select", which decides what SATA
50 * to one SATA adapter each, both acting as master, or one IDE
51 * blocks to two SATA adapters so the IDE block can act in a
55 * pins (not SATA pins) if (and only if) these are muxed in.
57 * 111-100 - Reserved
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H A Data_piix.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ata_piix.c - Intel PATA/SATA controllers
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
14 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
15 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
19 * as Documentation/driver-api/libata.rst
32 * change little except in gaining more modes until SATA arrives. This
34 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
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/linux/arch/arm/boot/dts/marvell/
H A Darmada-370-dlink-dns327l.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for D-Link DNS-327L
9 * There's still some unknown device on i2c address 0x13
12 /dts-v1/;
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include "armada-370.dtsi"
19 model = "D-Link DNS-327L";
22 "marvell,armada-370-xp";
25 stdout-path = &uart0;
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/linux/Documentation/devicetree/bindings/mips/cavium/
H A Dsata-uctl.txt1 * UCTL SATA controller glue
4 and the SATA AHCI host controller (UAHC). It performs the following functions:
5 - provides interfaces for the applications to access the UAHC AHCI
7 - provides a bridge for UAHC to fetch AHCI command table entries and data
9 - posts interrupts to the CIU.
10 - contains registers that:
11 - control the behavior of the UAHC
12 - control the clock/reset generation to UAHC
13 - control endian swapping for all UAHC registers and DMA accesses
17 - compatible: "cavium,octeon-7130-sata-uctl"
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/linux/Documentation/ABI/testing/
H A Dsysfs-block-device4 Contact: linux-ide@vger.kernel.org
12 0 OFF - the LED is not activated on activity
13 1 BLINK_ON - the LED blinks on every 10ms when activity is
15 2 BLINK_OFF - the LED is on when idle, and blinks off
26 Contact: linux-ide@vger.kernel.org
34 - If the device does not support the unload heads feature,
35 access is denied with -EOPNOTSUPP.
36 - The maximal value accepted for a timeout is 30000
38 - A previously set timeout can be cancelled and disk can resume
39 normal operation immediately by specifying a timeout of 0.
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