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Searched +full:s32g2 +full:- +full:siul2 +full:- +full:pinctrl (Results 1 – 4 of 4) sorted by relevance

/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnxp,s32g2-siul2-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul2-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: NXP S32G2 pin controller
11 - Ghennadi Procopciuc <Ghennadi.Procopciuc@oss.nxp.com>
12 - Chester Lin <chester62515@gmail.com>
15 S32G2 pinmux is implemented in SIUL2 (System Integration Unit Lite2),
20 Every SIUL2 region has multiple register types, and here only MSCR and
23 Please note that some register indexes are reserved in S32G2, such as
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/linux/arch/arm64/boot/dts/freescale/
H A Ds32g2.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * NXP S32G2 SoC family
6 * Copyright 2017-2021, 2024 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "nxp,s32g2";
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
18 #address-cells = <2>;
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H A Ds32g3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright 2021-2024 NXP
7 * Andra-Teodora Ilie <andra.ilie@nxp.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <0x02>;
16 #size-cells = <0x02>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 cpu-map {
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/linux/drivers/pinctrl/nxp/
H A Dpinctrl-s32g2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * NXP S32G pinctrl driver
5 * Copyright 2015-2016 Freescale Semiconductor, Inc.
6 * Copyright 2017-2018, 2020-2022 NXP
16 #include <linux/pinctrl/pinctrl.h>
18 #include "pinctrl-s32.h"
785 .compatible = "nxp,s32g2-siul2-pinctrl",
796 soc_data = of_device_get_match_data(&pdev->dev); in s32g_pinctrl_probe()
807 .name = "s32g-siul2-pinctrl",
817 MODULE_DESCRIPTION("NXP S32G pinctrl driver");