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Searched +full:rzg2l +full:- +full:usbphy +full:- +full:ctrl (Results 1 – 6 of 6) sorted by relevance

/linux/Documentation/devicetree/bindings/reset/
H A Drenesas,rzg2l-usbphy-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G2L,V2L} USBPHY Control
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 The RZ/G2L USBPHY Control mainly controls reset and power down of the
19 - enum:
20 - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five
21 - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
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/linux/drivers/reset/
H A Dreset-rzg2l-usbphy-ctrl.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/G2L USBPHY control driver
15 #include <linux/reset-controller.h>
49 void __iomem *base = priv->base; in rzg2l_usbphy_ctrl_assert()
53 spin_lock_irqsave(&priv->lock, flags); in rzg2l_usbphy_ctrl_assert()
59 spin_unlock_irqrestore(&priv->lock, flags); in rzg2l_usbphy_ctrl_assert()
68 void __iomem *base = priv->base; in rzg2l_usbphy_ctrl_deassert()
72 spin_lock_irqsave(&priv->lock, flags); in rzg2l_usbphy_ctrl_deassert()
78 spin_unlock_irqrestore(&priv->lock, flags); in rzg2l_usbphy_ctrl_deassert()
91 return !!(readl(priv->base + RESET) & port_mask); in rzg2l_usbphy_ctrl_status()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += core.o
3 obj-y += amlogic/
4 obj-y += hisilicon/
5 obj-y += starfive/
6 obj-y += sti/
7 obj-y += tegra/
8 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
9 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
10 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
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/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/r9a07g043-cpg.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 audio_clk1: audio1-clk {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
19 clock-frequency = <0>;
22 audio_clk2: audio2-clk {
23 compatible = "fixed-clock";
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H A Dr9a07g054.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
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H A Dr9a07g044.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
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