Searched +full:rzg2l +full:- +full:adc (Results 1 – 8 of 8) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Renesas RZ/G2L ADC10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>13 A/D Converter block is a successive approximation analog-to-digital converter14 with a 12-bit accuracy. Up to eight analog input channels can be selected.15 Conversions can be performed in single or repeat mode. Result of the ADC is16 stored in a 32-bit data register corresponding to each channel.[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/clock/r9a07g043-cpg.h>12 #address-cells = <2>;13 #size-cells = <2>;15 audio_clk1: audio1-clk {16 compatible = "fixed-clock";17 #clock-cells = <0>;19 clock-frequency = <0>;22 audio_clk2: audio2-clk {23 compatible = "fixed-clock";[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/clock/r9a07g054-cpg.h>13 #address-cells = <2>;14 #size-cells = <2>;16 audio_clk1: audio1-clk {17 compatible = "fixed-clock";18 #clock-cells = <0>;20 clock-frequency = <0>;23 audio_clk2: audio2-clk {[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/clock/r9a07g044-cpg.h>13 #address-cells = <2>;14 #size-cells = <2>;16 audio_clk1: audio1-clk {17 compatible = "fixed-clock";18 #clock-cells = <0>;20 clock-frequency = <0>;23 audio_clk2: audio2-clk {[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>28 reg_1p8v: regulator-1p8v {29 compatible = "regulator-fixed";30 regulator-name = "fixed-1.8V";31 regulator-min-microvolt = <1800000>;32 regulator-max-microvolt = <1800000>;33 regulator-boot-on;[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>38 reg_1p8v: regulator-1p8v {39 compatible = "regulator-fixed";40 regulator-name = "fixed-1.8V";41 regulator-min-microvolt = <1800000>;42 regulator-max-microvolt = <1800000>;43 regulator-boot-on;[all …]
1 // SPDX-License-Identifier: GPL-2.050 #define TS_CODE_CAP_TIMES 8 /* Total number of ADC data samples */67 return ioread32(priv->base + reg); in rzg2l_thermal_read()73 iowrite32(data, priv->base + reg); in rzg2l_thermal_write()109 val = ((dsensor - priv->calib1) * (MCELSIUS(165) / in rzg2l_thermal_get_temp()110 (priv->calib0 - priv->calib1))) - MCELSIUS(40); in rzg2l_thermal_get_temp()139 return readl_poll_timeout(priv->base + TSU_SS, reg_val, in rzg2l_thermal_init()146 struct rzg2l_thermal_priv *priv = dev_get_drvdata(&pdev->dev); in rzg2l_thermal_reset_assert_pm_disable_put()148 pm_runtime_put(&pdev->dev); in rzg2l_thermal_reset_assert_pm_disable_put()149 pm_runtime_disable(&pdev->dev); in rzg2l_thermal_reset_assert_pm_disable_put()[all …]
5 ---------------------------------------------------21 W: *Web-page* with status/info23 B: URI for where to file *bugs*. A web-page with detailed bug28 patches to the given subsystem. This is either an in-tree file,29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst46 N: [^a-z]tegra all files whose path contains tegra64 ----------------83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)85 L: linux-scsi@vger.kernel.org88 F: drivers/scsi/3w-*[all …]