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/linux/Documentation/devicetree/bindings/dma/
H A Drenesas,usb-dmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,usb-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13 - $ref: dma-controller.yaml#
18 - enum:
19 - renesas,r8a7742-usb-dmac # RZ/G1H
20 - renesas,r8a7743-usb-dmac # RZ/G1M
21 - renesas,r8a7744-usb-dmac # RZ/G1N
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H A Drenesas,rz-dmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ DMA Controller
10 - Biju Das <biju.das.jz@bp.renesas.com>
15 - items:
16 - enum:
17 - renesas,r7s72100-dmac # RZ/A1H
18 - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
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H A Drenesas,rcar-dmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rcar-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car and RZ/G DMA Controller
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13 - $ref: dma-controller.yaml#
18 - items:
19 - enum:
20 - renesas,dmac-r8a7742 # RZ/G1H
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/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/Five and RZ/G2UL SoCs
8 #include <dt-bindings/clock/r9a07g043-cpg.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 audio_clk1: audio1-clk {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
19 clock-frequency = <0>;
22 audio_clk2: audio2-clk {
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H A Dr9a07g044.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
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H A Dr9a07g054.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/V2L SoC
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
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/linux/drivers/dma/sh/
H A Drz-dmac.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/G2L DMA Controller Driver
5 * Based on imx-dma.c
9 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
13 #include <linux/dma-mapping.h>
17 #include <linux/irqchip/irq-renesas-rzv2h.h>
30 #include "../virt-dma.h"
117 * -----------------------------------------------------------------------------
179 /* RZ/V2H ICU related */
183 * -----------------------------------------------------------------------------
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_SH_DMAE_BASE) += shdma-base.o
12 shdma-y := shdmac.o
13 shdma-objs := $(shdma-y)
14 obj-$(CONFIG_SH_DMAE) += shdma.o
16 obj-$(CONFIG_RCAR_DMAC) += rcar-dmac.o
17 obj-$(CONFIG_RENESAS_USB_DMAC) += usb-dmac.o
18 obj-$(CONFIG_RZ_DMAC) += rz-dmac.o
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
29 tristate "Renesas SuperH DMAC support"
35 tristate "Renesas R-Car Gen{2,3} and RZ/G{1,2} DMA Controller"
40 Renesas R-Car Gen{2,3} and RZ/G{1,2} SoCs.
43 tristate "Renesas USB-DMA Controller"
48 This driver supports the USB-DMA controller found in the Renesas
52 tristate "Renesas RZ DMA Controller"
58 found in the Renesas RZ SoC variants.
/linux/Documentation/devicetree/bindings/soc/renesas/
H A Drenesas,r9a09g011-sys.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g011-sys.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/V2M System Configuration (SYS)
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The RZ/V2M-alike SYS (System Configuration) controls the overall
15 - Bank address settings for DMAC
16 - Bank address settings of the units for ICB
17 - ETHER AxCACHE[1] (C bit) control function
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H A Drenesas-soc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/renesas/renesas-soc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
16 renesas,SoC-IP
19 renesas,r8a77965-csi2
28 pattern: "^renesas,.+-.+$"
30 - compatible
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/linux/drivers/net/ethernet/renesas/
H A Dravb.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 2014-2015 Renesas Electronics Corporation
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
17 #include <linux/mdio-bitbang.h>
49 /* AVB-DMAC registers */
77 APSR = 0x008C, /* R-Car Gen3 only */
85 RTC = 0x00B4, /* R-Car Gen3 and RZ/G2L only */
160 CIE = 0x0384, /* R-Car Gen3 only */
170 GCPT = 0x03B4, /* Documented for R-Car Gen3 only */
174 GIE = 0x03CC, /* R-Car Gen3 only */
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/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,cpg-mstp-clocks.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
23 - enum:
24 - renesas,r7s72100-mstp-clocks # RZ/A1
25 - renesas,r8a73a4-mstp-clocks # R-Mobile APE6
26 - renesas,r8a7740-mstp-clocks # R-Mobile A1
27 - renesas,r8a7778-mstp-clocks # R-Car M1
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/linux/drivers/dma/dw/
H A Drzn1-dmamux.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2022 Schneider-Electric
13 #include <linux/soc/renesas/r9a06g032-sysctrl.h>
34 dev_dbg(dev, "Unmapping DMAMUX request %u\n", map->req_idx); in rzn1_dmamux_free()
36 clear_bit(map->req_idx, dmamux->used_chans); in rzn1_dmamux_free()
44 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); in rzn1_dmamux_route_allocate()
51 if (dma_spec->args_count != RNZ1_DMAMUX_NCELLS) { in rzn1_dmamux_route_allocate()
52 ret = -EINVAL; in rzn1_dmamux_route_allocate()
58 ret = -ENOMEM; in rzn1_dmamux_route_allocate()
62 chan = dma_spec->args[0]; in rzn1_dmamux_route_allocate()
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/linux/drivers/spi/
H A Dspi-rspi.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on spi-sh.c:
21 #include <linux/dma-mapping.h>
40 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
55 /* RSPI on RZ only */
68 /* SPCR - Control Register */
77 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
78 /* QSPI on R-Car Gen2 only */
79 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
80 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
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/linux/drivers/clk/renesas/
H A Dr8a7743-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/soc/renesas/rcar-rst.h>
14 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
16 #include "renesas-cpg-mssr.h"
17 #include "rcar-gen2-cpg.h"
86 DEF_MOD("2d-dmac", 115, R8A7743_CLK_ZS),
87 DEF_MOD("fdp1-1", 118, R8A7743_CLK_ZS),
88 DEF_MOD("fdp1-0", 119, R8A7743_CLK_ZS),
104 DEF_MOD("sys-dmac1", 218, R8A7743_CLK_ZS),
105 DEF_MOD("sys-dmac0", 219, R8A7743_CLK_ZS),
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/linux/drivers/irqchip/
H A Dirq-renesas-rzv2h.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/V2H(P) ICU Driver
5 * Based on irq-renesas-rzg2l.c
17 #include <linux/irqchip/irq-renesas-rzv2h.h>
71 ICU_TSSR_TSSEL_PREP((GENMASK(((_field_width) - 2), 0)), (n), _field_width); \
77 BIT((_field_width) - 1) << ((n) * (_field_width)); \
93 * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
106 /* DMAC */
116 * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure.
142 guard(raw_spinlock_irqsave)(&priv->lock); in rzv2h_icu_register_dma_req()
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/linux/drivers/usb/gadget/udc/
H A Drenesas_usb3.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
11 #include <linux/dma-mapping.h>
13 #include <linux/extcon-provider.h>
37 #define USB3_DMA_CH0_CON(n) (0x030 + ((n) - 1) * 0x10) /* n = 1 to 4 */
38 #define USB3_DMA_CH0_PRD_ADR(n) (0x034 + ((n) - 1) * 0x10) /* n = 1 to 4 */
43 #define USB3_DRD_CON(p) ((p)->is_rzv2m ? 0x400 : 0x218)
50 #define USB3_USB_OTG_STA(p) ((p)->is_rzv2m ? 0x410 : 0x268)
51 #define USB3_USB_OTG_INT_STA(p) ((p)->is_rzv2m ? 0x414 : 0x26c)
52 #define USB3_USB_OTG_INT_ENA(p) ((p)->is_rzv2m ? 0x418 : 0x270)
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