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/illumos-gate/usr/src/uts/common/io/e1000api/
H A De1000_regs.h84 #define E1000_RCTL 0x00100 /* Rx Control - RW */
87 #define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */
144 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
148 #define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
149 #define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
150 #define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
151 #define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
152 #define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
153 #define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */
155 /* Split and Replication Rx Control - RW */
[all …]
/illumos-gate/usr/src/common/crypto/ecc/
H A Dec2_test.c149 mp_int one, order_1, gx, gy, rx, ry, n; in ectest_curve_GF2m() local
159 MP_CHECKOK(mp_init(&rx, kmflag)); in ectest_curve_GF2m()
195 (&order_1, &group->genx, &group->geny, &rx, &ry, group)); in ectest_curve_GF2m()
198 MP_CHECKOK(mp_toradix(&rx, s, 16)); in ectest_curve_GF2m()
203 MP_CHECKOK(group->meth->field_add(&ry, &rx, &ry, group->meth)); in ectest_curve_GF2m()
204 if ((mp_cmp(&rx, &group->genx) != 0) in ectest_curve_GF2m()
215 (&order_1, &group->genx, &group->geny, &rx, &ry, group)); in ectest_curve_GF2m()
218 MP_CHECKOK(mp_toradix(&rx, s, 16)); in ectest_curve_GF2m()
223 MP_CHECKOK(group->meth->field_add(&ry, &rx, &ry, group->meth)); in ectest_curve_GF2m()
224 if ((mp_cmp(&rx, &group->genx) != 0) in ectest_curve_GF2m()
[all …]
H A Decp_jac.c60 * projective coordinates R(rx, ry, rz). Assumes input is already
64 ec_GFp_pt_aff2jac(const mp_int *px, const mp_int *py, mp_int *rx, in ec_GFp_pt_aff2jac() argument
70 MP_CHECKOK(ec_GFp_pt_set_inf_jac(rx, ry, rz)); in ec_GFp_pt_aff2jac()
72 MP_CHECKOK(mp_copy(px, rx)); in ec_GFp_pt_aff2jac()
84 * affine coordinates R(rx, ry). P and R can share x and y coordinates.
89 mp_int *rx, mp_int *ry, const ECGroup *group) in ec_GFp_pt_jac2aff() argument
103 MP_CHECKOK(ec_GFp_pt_set_inf_aff(rx, ry)); in ec_GFp_pt_jac2aff()
109 MP_CHECKOK(mp_copy(px, rx)); in ec_GFp_pt_jac2aff()
115 MP_CHECKOK(group->meth->field_mul(px, &z2, rx, group->meth)); in ec_GFp_pt_jac2aff()
143 /* Computes R = P + Q where R is (rx, ry, rz), P is (px, py, pz) and Q is
[all …]
H A Decp_jm.c63 const mp_int *paz4, mp_int *rx, mp_int *ry, mp_int *rz, in ec_GFp_pt_dbl_jm() argument
82 MP_CHECKOK(ec_GFp_pt_set_inf_jac(rx, ry, rz)); in ec_GFp_pt_dbl_jm()
107 /* rx = M^2 - 2S */ in ec_GFp_pt_dbl_jm()
108 MP_CHECKOK(group->meth->field_sqr(M, rx, group->meth)); in ec_GFp_pt_dbl_jm()
109 MP_CHECKOK(group->meth->field_sub(rx, S, rx, group->meth)); in ec_GFp_pt_dbl_jm()
110 MP_CHECKOK(group->meth->field_sub(rx, S, rx, group->meth)); in ec_GFp_pt_dbl_jm()
112 /* ry = M * (S - rx) - t1 */ in ec_GFp_pt_dbl_jm()
113 MP_CHECKOK(group->meth->field_sub(S, rx, S, group->meth)); in ec_GFp_pt_dbl_jm()
126 /* Computes R = P + Q where R is (rx, ry, rz), P is (px, py, pz) and Q is
134 const mp_int *qy, mp_int *rx, mp_int *ry, mp_int *rz, in ec_GFp_pt_add_jm_aff() argument
[all …]
H A Decp_test.c148 mp_int one, order_1, gx, gy, rx, ry, n; in ectest_curve_GFp() local
158 MP_CHECKOK(mp_init(&rx, kmflag)); in ectest_curve_GFp()
193 (&order_1, &group->genx, &group->geny, &rx, &ry, group)); in ectest_curve_GFp()
196 MP_CHECKOK(mp_toradix(&rx, s, 16)); in ectest_curve_GFp()
202 if ((mp_cmp(&rx, &group->genx) != 0) in ectest_curve_GFp()
214 (&order_1, &group->genx, &group->geny, &rx, &ry, group)); in ectest_curve_GFp()
217 MP_CHECKOK(mp_toradix(&rx, s, 16)); in ectest_curve_GFp()
223 if ((mp_cmp(&rx, &group->genx) != 0) in ectest_curve_GFp()
233 MP_CHECKOK(ECPoint_mul(group, &order_1, NULL, NULL, &rx, &ry)); in ectest_curve_GFp()
236 MP_CHECKOK(mp_toradix(&rx, s, 16)); in ectest_curve_GFp()
[all …]
H A Decl_mult.c59 const mp_int *py, mp_int *rx, mp_int *ry) in ECPoint_mul() argument
80 MP_CHECKOK(group->base_point_mul(&kt, rx, ry, group)); in ECPoint_mul()
83 point_mul(&kt, &group->genx, &group->geny, rx, ry, in ECPoint_mul()
88 MP_CHECKOK(group->meth->field_enc(px, rx, group->meth)); in ECPoint_mul()
90 MP_CHECKOK(group->point_mul(&kt, rx, ry, rx, ry, group)); in ECPoint_mul()
92 MP_CHECKOK(group->point_mul(&kt, px, py, rx, ry, group)); in ECPoint_mul()
96 MP_CHECKOK(group->meth->field_dec(rx, rx, group->meth)); in ECPoint_mul()
113 const mp_int *py, mp_int *rx, mp_int *ry, in ec_pts_mul_basic() argument
126 return ECPoint_mul(group, k2, px, py, rx, ry); in ec_pts_mul_basic()
128 return ECPoint_mul(group, k1, NULL, NULL, rx, ry); in ec_pts_mul_basic()
[all …]
H A Decp.h56 /* Computes R = P + Q where R is (rx, ry), P is (px, py) and Q is (qx,
59 const mp_int *qx, const mp_int *qy, mp_int *rx,
64 const mp_int *qx, const mp_int *qy, mp_int *rx,
68 mp_err ec_GFp_pt_dbl_aff(const mp_int *px, const mp_int *py, mp_int *rx,
75 /* Computes R = nP where R is (rx, ry) and P is (px, py). The parameters
79 const mp_int *py, mp_int *rx, mp_int *ry,
84 * projective coordinates R(rx, ry, rz). */
85 mp_err ec_GFp_pt_aff2jac(const mp_int *px, const mp_int *py, mp_int *rx,
89 * affine coordinates R(rx, ry). */
91 const mp_int *pz, mp_int *rx, mp_int *ry,
[all …]
H A Dec2.h56 /* Computes R = P + Q where R is (rx, ry), P is (px, py) and Q is (qx,
59 const mp_int *qx, const mp_int *qy, mp_int *rx,
64 const mp_int *qx, const mp_int *qy, mp_int *rx,
68 mp_err ec_GF2m_pt_dbl_aff(const mp_int *px, const mp_int *py, mp_int *rx,
76 /* Computes R = nP where R is (rx, ry) and P is (px, py). The parameters
80 const mp_int *py, mp_int *rx, mp_int *ry,
84 /* Computes R = nP where R is (rx, ry) and P is (px, py). The parameters
88 const mp_int *py, mp_int *rx, mp_int *ry,
93 * coordinates R(rx, ry, rz). */
94 mp_err ec_GF2m_pt_aff2proj(const mp_int *px, const mp_int *py, mp_int *rx,
[all …]
/illumos-gate/usr/src/uts/common/io/igc/core/
H A Digc_regs.h35 #define IGC_RCTL 0x00100 /* Rx Control - RW */
38 #define IGC_RXCW 0x00180 /* Rx Configuration Word - RO */
68 #define IGC_ERT 0x02008 /* Early Rx Threshold - RW */
72 #define IGC_RDFH 0x02410 /* Rx Data FIFO Head - RW */
73 #define IGC_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
74 #define IGC_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
75 #define IGC_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
76 #define IGC_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
77 #define IGC_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */
79 /* Split and Replication Rx Control - RW */
[all …]
/illumos-gate/usr/src/uts/common/io/fibre-channel/fca/oce/
H A Doce_stat.c63 port_stats = &dev->hw_stats->params.rsp.rx.port[dev->port_id]; in oce_update_stats()
155 dev->hw_stats->params.rsp.rx.rx_drops_no_pbuf; in oce_update_stats()
157 dev->hw_stats->params.rsp.rx.rx_drops_no_txpb; in oce_update_stats()
159 dev->hw_stats->params.rsp.rx.rx_drops_no_erx_descr; in oce_update_stats()
161 dev->hw_stats->params.rsp.rx.rx_drops_no_tpre_descr; in oce_update_stats()
163 dev->hw_stats->params.rsp.rx.rx_drops_too_many_frags; in oce_update_stats()
165 dev->hw_stats->params.rsp.rx.rx_drops_invalid_ring; in oce_update_stats()
167 dev->hw_stats->params.rsp.rx.rx_drops_mtu; in oce_update_stats()
227 kstat_named_init(&stats->rx_bytes_hi, "rx bytes msd", KSTAT_DATA_ULONG); in oce_stat_init()
228 kstat_named_init(&stats->rx_bytes_lo, "rx bytes lsd", KSTAT_DATA_ULONG); in oce_stat_init()
[all …]
/illumos-gate/usr/src/uts/common/io/bfe/
H A Dbfe_hw.h60 #define BFE_ISTAT_RX 0x00010000 /* RX Interrupt */
113 #define BFE_DMARX_CTRL 0x00000210 /* DMA RX Control */
118 #define BFE_DMARX_ADDR 0x00000214 /* DMA RX Descriptor Ring Address */
119 #define BFE_DMARX_PTR 0x00000218 /* DMA RX Last Posted Descriptor */
120 #define BFE_DMARX_STAT 0x0000021C /* DMA RX Current Active Desc. + Status */
122 #define BFE_RXCONF 0x00000400 /* EMAC RX Config */
132 #define BFE_RXMAXLEN 0x00000404 /* EMAC RX Max Packet Length */
218 #define BFE_RX_GOOD_O 0x00000580 /* MIB RX Good Octets */
219 #define BFE_RX_GOOD_P 0x00000584 /* MIB RX Good Packets */
220 #define BFE_RX_O 0x00000588 /* MIB RX Octets */
[all …]
/illumos-gate/usr/src/uts/common/io/hxge/
H A Dhxge_vmac_hw.h61 * Write a '1' to reset Rx VMAC; auto clears. This brings rx vmac
137 * Rx VMAC Configuration
141 * Maximum length of a frame accepted by Rx/Tx VMAC. Only packets
143 * accepted by Rx/Tx VMAC. This length indicates just the packet
155 * FCS value are dropped by Rx VMAC.
156 * Enable rx VMAC. Write a '1' to enable rx VMAC; write a '0' to
258 * Rx VMAC Status Register
261 * Rx VMAC is enabled by vmacRxCfg::rxEn=1. Disabling Rx VMAC does
317 * Rx VMAC Status Mask
404 * Rx VMAC Status Mirror Register
[all …]
H A Dhxge_rdc_hw.h752 * Rx DMA Packet Counter
753 * Description: Counts the number of packets received from the Rx
776 * Rx DMA Dropped Packet Counters
789 * rx ram. This counter saturates.
817 * Rx DMA Byte Counter
839 * Rx DMA Prefetch Buffer Command
882 * Rx DMA Prefetch Buffer Data
908 * Rx DMA Shadow Tail Command
950 * Rx DMA Shadow Tail Data
972 * Rx DMA Shadow Tail Parity Data
[all …]
/illumos-gate/usr/src/uts/common/io/bnx/
H A Dbnxrcv.c76 * size plus room for a small, 16 byte inline rx buffer descriptor in bnx_rxbuffer_alloc()
80 pktsize = lmpacket->u1.rx.buf_size; in bnx_rxbuffer_alloc()
84 (void *)0, (caddr_t *)&lmpacket->u1.rx.mem_virt, &reallen, in bnx_rxbuffer_alloc()
92 (caddr_t)lmpacket->u1.rx.mem_virt, pktsize, in bnx_rxbuffer_alloc()
99 lmpacket->u1.rx.mem_phy.as_u64 = cookie.dmac_laddress; in bnx_rxbuffer_alloc()
119 lmpacket->u1.rx.mem_phy.as_u64 = 0; in bnx_rxbuffer_free()
120 lmpacket->u1.rx.buf_size = 0; in bnx_rxbuffer_free()
124 lmpacket->u1.rx.mem_virt = NULL; in bnx_rxbuffer_free()
240 /* Send the rx packets up. */ in bnx_recv_ring_recv()
269 * // The LM will need access to the complete rx buffer. in bnx_recv_ring_recv()
[all …]
/illumos-gate/usr/src/uts/common/io/nxge/
H A Dnxge_hv.c54 nxhv_dc_fp_t *rx; in nxge_hio_hv_init() local
85 rx = &nhd->hio.rx; in nxge_hio_hv_init()
87 rx->assign = &hv_niu_rx_dma_assign; in nxge_hio_hv_init()
88 rx->unassign = &hv_niu_rx_dma_unassign; in nxge_hio_hv_init()
89 rx->get_map = &hv_niu_vr_get_rxmap; in nxge_hio_hv_init()
92 rx->lp_conf = &hv_niu_rx_logical_page_conf; in nxge_hio_hv_init()
93 rx->lp_info = &hv_niu_rx_logical_page_info; in nxge_hio_hv_init()
95 rx->lp_cfgh_conf = &hv_niu_cfgh_rx_logical_page_conf; in nxge_hio_hv_init()
96 rx->lp_cfgh_info = &hv_niu_cfgh_rx_logical_page_info; in nxge_hio_hv_init()
98 rx->getinfo = &hv_niu_vrrx_getinfo; in nxge_hio_hv_init()
/illumos-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_rxdma.h53 * RX NPI error codes
207 * rdc: RX DMA Channel number
319 * init the clock division, used for RX timers
320 * This determines the granularity of RX DMA countdown timers
384 * rdc: RX DMA Channel number
457 * rdc: RX DMA Channel number
481 * rdc: RX DMA Channel number
524 * rdc: RX DMA Channel number
566 * Forces RX completion ring update
569 * rdc: RX DMA Channel number
[all …]
/illumos-gate/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/
H A Dbnx_lm_recv.c119 ((u32_t *) packet->u1.rx.mem_virt)[0] = 0; in lm_post_buffers()
120 ((u32_t *) packet->u1.rx.mem_virt)[1] = 0; in lm_post_buffers()
121 ((u32_t *) packet->u1.rx.mem_virt)[2] = 0; in lm_post_buffers()
122 ((u32_t *) packet->u1.rx.mem_virt)[3] = 0; in lm_post_buffers()
124 packet->u1.rx.dbg_bd = cur_bd; in lm_post_buffers()
130 packet->u1.rx.mem_phy.as_u64, in lm_post_buffers()
131 packet->u1.rx.buf_size); in lm_post_buffers()
132 rxq->prod_bseq += packet->u1.rx.buf_size; in lm_post_buffers()
133 packet->u1.rx.next_bd_idx = rxq->prod_idx; in lm_post_buffers()
217 pkt->u1.rx.mem_virt, in get_packets_rcvd()
[all …]
/illumos-gate/usr/src/uts/common/io/ixgbe/
H A Dixgbe_sw.h281 uint32_t max_rx_que_num; /* maximum number of rx queues */
282 uint32_t min_rx_que_num; /* minimum number of rx queues */
283 uint32_t def_rx_que_num; /* default number of rx queues */
284 uint32_t max_rx_grp_num; /* maximum number of rx groups */
285 uint32_t min_rx_grp_num; /* minimum number of rx groups */
286 uint32_t def_rx_grp_num; /* default number of rx groups */
306 /* bits representing all interrupt types other than tx & rx */
396 * The list of VLANs an Rx group will accept.
457 * RX Control Block
550 * Rx descriptor ring definitions
[all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/l4/
H A Dlm_l4rx.c88 gen_info = &tcp->rx_con->u.rx.gen_info; in _lm_tcp_isle_find()
120 gen_info = &tcp->rx_con->u.rx.gen_info; in _lm_tcp_isle_remove()
200 volatile struct toe_rx_db_data *db_data = rx_con->db_data.rx; in lm_tcp_rx_write_db()
237 volatile struct toe_rx_db_data *db_data = rx_con->db_data.rx; in lm_tcp_rx_post_sws()
243 …n_right_edge=%d FW right_edge=%d \n", rx_con->u.rx.sws_info.drv_rcv_win_right_edge, nbytes, rx_con… in lm_tcp_rx_post_sws()
244 if (rx_con->u.rx.sws_info.extra_bytes > nbytes) { in lm_tcp_rx_post_sws()
245 rx_con->u.rx.sws_info.extra_bytes -= nbytes; in lm_tcp_rx_post_sws()
248 nbytes -= rx_con->u.rx.sws_info.extra_bytes; in lm_tcp_rx_post_sws()
249 rx_con->u.rx.sws_info.extra_bytes = 0; in lm_tcp_rx_post_sws()
250 rx_con->u.rx.sws_info.drv_rcv_win_right_edge += nbytes; in lm_tcp_rx_post_sws()
[all …]
/illumos-gate/usr/src/grub/grub-0.97/netboot/
H A De1000_hw.h386 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
582 #define E1000_RCTL 0x00100 /* RX Control - RW */
585 #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
594 #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
595 #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
596 #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
597 #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
598 #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
599 #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
600 #define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
[all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/mcp/
H A Dmac_drv_info.h86 u32 rxq_size; /* RX Descriptors Queue Size */
89 /* RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */
107 u32 rxq_size; /* FCoE RX Descriptors Queue Size. */
110 /* FCoE RX Descriptors Queue Avg Depth. */
112 u32 rx_frames_lo; /* FCoE RX Frames received. */
113 u32 rx_frames_hi; /* FCoE RX Frames received. */
114 u32 rx_bytes_lo; /* FCoE RX Bytes received. */
115 u32 rx_bytes_hi; /* FCoE RX Bytes received. */
144 u32 rxq_size; /* PDU RX Descriptors Queue Size. */
147 u32 rxq_avg_depth; /*PDU RX Descriptors Queue Avg Depth. */
[all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/
H A Decore_phy.c458 {0x00000000, "GRX64","RX 64-byte frame counter" },
459 {0x00000001, "GRX127","RX 65 to 127 byte frame counter" },
460 {0x00000002, "GRX255","RX 128 to 255 byte frame counter" },
461 {0x00000003, "GRX511","RX 256 to 511 byte frame counter" },
462 {0x00000004, "GRX1023","RX 512 to 1023 byte frame counter" },
463 {0x00000005, "GRX1518","RX 1024 to 1518 byte frame counter" },
464 {0x00000006, "GRX1522","RX 1519 to 1522 byte VLAN-tagged frame counter" },
465 {0x00000007, "GRX2047","RX 1519 to 2047 byte frame counter" },
466 {0x00000008, "GRX4095","RX 2048 to 4095 byte frame counter" },
467 {0x00000009, "GRX9216","RX 4096 to 9216 byte frame counter" },
[all …]
/illumos-gate/usr/src/uts/common/io/udmf/
H A Ddm9601reg.h18 #define RCR 0x05U /* rx control register */
19 #define RSR 0x06U /* rx status register */
20 #define ROCR 0x07U /* rx overflow counter register */
71 #define NSR_RXOV 0x02U /* rx fifo overflow */
72 #define NSR_RXRDY 0x01U /* rx packet ready */
119 /* rx control register */
126 #define RCR_RXEN 0x01U /* rx enable */
138 /* rx status register */
192 #define FCTR_HWOT 0xf0U /* rx fifo high water overflow threshold */
195 #define FCTR_LWOT 0x0fU /* rx fifo low water overflow threshold */
[all …]
/illumos-gate/usr/src/uts/common/io/igb/
H A Digb_sw.h323 uint32_t max_rx_que_num; /* maximum number of rx queues */
324 uint32_t min_rx_que_num; /* minimum number of rx queues */
325 uint32_t def_rx_que_num; /* default number of rx queues */
401 * RX Control Block
495 * Rx descriptor ring definitions
497 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */
498 union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */
499 uint32_t rbd_next; /* Index of next rx desc */
502 * Rx control block list definitions
512 * Rx sw ring settings and status
[all …]
/illumos-gate/usr/src/uts/common/io/hme/
H A Dhme_mac.h96 #define HMERMD_OVFLOW (1 << 30) /* 30 : Rx buffer overflow */
170 #define HMEG_STATUS_RX_DROP (1 << 17) /* No free Rx descriptors */
171 #define HMEG_STATUS_RX_ERR_ACK (1 << 18) /* Error Ack in Rx DMA cycle */
172 #define HMEG_STATUS_RX_LATE_ERR (1 << 19) /* Late Error in Rx DMA cycle */
173 #define HMEG_STATUS_RX_PAR_ERR (1 << 20) /* Parity error in Rx DMA */
224 #define HMEG_MASK_RX_DROP (1 << 17) /* No free Rx descriptors */
225 #define HMEG_MASK_RX_ERR_ACK (1 << 18) /* Error Ack in Rx DMA cycle */
226 #define HMEG_MASK_RX_LATE_ERR (1 << 19) /* Late Error in Rx DMA cycle */
227 #define HMEG_MASK_RX_PAR_ERR (1 << 20) /* Parity error in Rx DMA */
341 #define HMER_CONFIG_RXDMA_EN (1 << 0) /* 0 : Enable Rx DMA */
[all …]

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