Lines Matching full:rx
162 #define CDC_RX_RXn_RX_PATH_CTL(rx, n) (0x0400 + rx->rxn_reg_stride * n) argument
170 #define CDC_RX_RXn_RX_PATH_CFG0(rx, n) (0x0404 + rx->rxn_reg_stride * n) argument
177 #define CDC_RX_RXn_RX_PATH_CFG1(rx, n) (0x0408 + rx->rxn_reg_stride * n) argument
181 #define CDC_RX_RXn_RX_PATH_CFG2(rx, n) (0x040C + rx->rxn_reg_stride * n) argument
184 #define CDC_RX_RXn_RX_PATH_CFG3(rx, n) (0x0410 + rx->rxn_reg_stride * n) argument
188 #define CDC_RX_RXn_RX_VOL_CTL(rx, n) (0x0414 + rx->rxn_reg_stride * n) argument
190 #define CDC_RX_RXn_RX_PATH_MIX_CTL(rx, n) (0x0418 + rx->rxn_reg_stride * n) argument
197 #define CDC_RX_RXn_RX_VOL_MIX_CTL(rx, n) (0x0420 + rx->rxn_reg_stride * n) argument
202 #define CDC_RX_RXn_RX_PATH_SEC3(rx, n) (0x042c + rx->rxn_reg_stride * n) argument
205 #define CDC_RX_RXn_RX_PATH_SEC7(rx, n) \ argument
206 (0x0434 + (rx->rxn_reg_stride * n) + ((n > 1) ? rx->rxn_reg_stride2 : 0))
211 #define CDC_RX_RXn_RX_PATH_DSM_CTL(rx, n) \ argument
212 (0x0440 + (rx->rxn_reg_stride * n) + ((n > 1) ? rx->rxn_reg_stride2 : 0))
221 /* RX offsets prior to 2.5 codec version */
269 /* LPASS CODEC version 2.5 rx reg offsets */
703 "ZERO", "RX INT0_1 MIX1",
707 "ZERO", "RX INT1_1 MIX1",
711 "ZERO", "RX INT2_1 MIX1",
715 "ZERO", "RX INT0_2 MUX",
719 "ZERO", "RX INT1_2 MUX",
723 "ZERO", "RX INT2_2 MUX",
823 SOC_DAPM_ENUM("RX MIX TX1_MUX Mux", rx_mix_tx1_mux_enum);
825 SOC_DAPM_ENUM("RX MIX TX2_MUX Mux", rx_mix_tx2_mux_enum);
885 SOC_DAPM_ENUM("RX MIX TX0_MUX Mux", rx_mix_tx0_mux_enum);
888 /* RX Macro */
1242 /* Update volatile list for rx/tx macros */ in rx_is_volatile_register()
1386 struct rx_macro *rx = dev_get_drvdata(dev); in rx_is_rw_register() local
1603 switch (rx->codec_version) { in rx_is_rw_register()
1686 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_int_dem_inp_mux_put() local
1693 if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 0)) in rx_macro_int_dem_inp_mux_put()
1694 look_ahead_dly_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 0); in rx_macro_int_dem_inp_mux_put()
1695 else if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 1)) in rx_macro_int_dem_inp_mux_put()
1696 look_ahead_dly_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 1); in rx_macro_int_dem_inp_mux_put()
1731 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_set_prim_interpolator_rate() local
1733 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { in rx_macro_set_prim_interpolator_rate()
1738 * to which interpolator input, the rx port in rx_macro_set_prim_interpolator_rate()
1754 int_fs_reg = CDC_RX_RXn_RX_PATH_CTL(rx, j); in rx_macro_set_prim_interpolator_rate()
1776 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_set_mix_interpolator_rate() local
1778 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { in rx_macro_set_mix_interpolator_rate()
1787 int_fs_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, j); in rx_macro_set_mix_interpolator_rate()
1822 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_hw_params() local
1833 rx->bit_width[dai->id] = params_width(params); in rx_macro_hw_params()
1846 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_channel_map() local
1854 for_each_set_bit(temp, &rx->active_ch_mask[dai->id], in rx_macro_get_channel_map()
1875 *rx_num = rx->active_ch_cnt[dai->id]; in rx_macro_get_channel_map()
1906 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_digital_mute() local
1917 reg = CDC_RX_RXn_RX_PATH_CTL(rx, j); in rx_macro_digital_mute()
1918 mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, j); in rx_macro_digital_mute()
1919 dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, j); in rx_macro_digital_mute()
2036 static void rx_macro_mclk_enable(struct rx_macro *rx, bool mclk_enable) in rx_macro_mclk_enable() argument
2038 struct regmap *regmap = rx->regmap; in rx_macro_mclk_enable()
2041 if (rx->rx_mclk_users == 0) { in rx_macro_mclk_enable()
2055 rx->rx_mclk_users++; in rx_macro_mclk_enable()
2057 if (rx->rx_mclk_users <= 0) { in rx_macro_mclk_enable()
2058 dev_err(rx->dev, "%s: clock already disabled\n", __func__); in rx_macro_mclk_enable()
2059 rx->rx_mclk_users = 0; in rx_macro_mclk_enable()
2062 rx->rx_mclk_users--; in rx_macro_mclk_enable()
2063 if (rx->rx_mclk_users == 0) { in rx_macro_mclk_enable()
2080 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_mclk_event() local
2085 rx_macro_mclk_enable(rx, true); in rx_macro_mclk_event()
2088 rx_macro_mclk_enable(rx, false); in rx_macro_mclk_event()
2141 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_enable_main_path() local
2144 reg = CDC_RX_RXn_RX_PATH_CTL(rx, w->shift); in rx_macro_enable_main_path()
2145 gain_reg = CDC_RX_RXn_RX_VOL_CTL(rx, w->shift); in rx_macro_enable_main_path()
2168 struct rx_macro *rx, in rx_macro_config_compander() argument
2177 pcm_rate = snd_soc_component_read(component, CDC_RX_RXn_RX_PATH_CTL(rx, comp)) & 0x0F; in rx_macro_config_compander()
2188 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, comp), in rx_macro_config_compander()
2192 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, comp), in rx_macro_config_compander()
2194 if (!rx->comp_enabled[comp]) in rx_macro_config_compander()
2205 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(rx, comp), in rx_macro_config_compander()
2212 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(rx, comp), in rx_macro_config_compander()
2224 struct rx_macro *rx, in rx_macro_load_compander_coeff() argument
2235 if (!rx->comp_enabled[comp]) in rx_macro_load_compander_coeff()
2249 hph_pwr_mode = rx->hph_pwr_mode; in rx_macro_load_compander_coeff()
2265 struct rx_macro *rx, bool enable) in rx_macro_enable_softclip_clk() argument
2268 if (rx->softclip_clk_users == 0) in rx_macro_enable_softclip_clk()
2271 rx->softclip_clk_users++; in rx_macro_enable_softclip_clk()
2273 rx->softclip_clk_users--; in rx_macro_enable_softclip_clk()
2274 if (rx->softclip_clk_users == 0) in rx_macro_enable_softclip_clk()
2281 struct rx_macro *rx, int event) in rx_macro_config_softclip() argument
2284 if (!rx->is_softclip_on) in rx_macro_config_softclip()
2289 rx_macro_enable_softclip_clk(component, rx, true); in rx_macro_config_softclip()
2298 rx_macro_enable_softclip_clk(component, rx, false); in rx_macro_config_softclip()
2305 struct rx_macro *rx, int event) in rx_macro_config_aux_hpf() argument
2309 if (!rx->is_aux_hpf_on) in rx_macro_config_aux_hpf()
2311 CDC_RX_RXn_RX_PATH_CFG1(rx, 2), 0x04, 0x00); in rx_macro_config_aux_hpf()
2317 CDC_RX_RXn_RX_PATH_CFG1(rx, 2), 0x04, 0x04); in rx_macro_config_aux_hpf()
2323 static inline void rx_macro_enable_clsh_block(struct rx_macro *rx, bool enable) in rx_macro_enable_clsh_block() argument
2325 if ((enable && ++rx->clsh_users == 1) || (!enable && --rx->clsh_users == 0)) in rx_macro_enable_clsh_block()
2326 snd_soc_component_update_bits(rx->component, CDC_RX_CLSH_CRC, in rx_macro_enable_clsh_block()
2328 if (rx->clsh_users < 0) in rx_macro_enable_clsh_block()
2329 rx->clsh_users = 0; in rx_macro_enable_clsh_block()
2333 struct rx_macro *rx, in rx_macro_config_classh() argument
2337 rx_macro_enable_clsh_block(rx, false); in rx_macro_config_classh()
2344 rx_macro_enable_clsh_block(rx, true); in rx_macro_config_classh()
2357 if (rx->is_ear_mode_on) in rx_macro_config_classh()
2369 CDC_RX_RXn_RX_PATH_CFG0(rx, 0), in rx_macro_config_classh()
2373 if (rx->is_ear_mode_on) in rx_macro_config_classh()
2385 CDC_RX_RXn_RX_PATH_CFG0(rx, 1), in rx_macro_config_classh()
2390 CDC_RX_RXn_RX_PATH_CFG0(rx, 2), in rx_macro_config_classh()
2393 CDC_RX_RXn_RX_PATH_CFG0(rx, 2), in rx_macro_config_classh()
2404 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_hd2_control() local
2409 hd2_scale_reg = CDC_RX_RXn_RX_PATH_SEC3(rx, 0); in rx_macro_hd2_control()
2410 hd2_enable_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 0); in rx_macro_hd2_control()
2413 hd2_scale_reg = CDC_RX_RXn_RX_PATH_SEC3(rx, 1); in rx_macro_hd2_control()
2414 hd2_enable_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 1); in rx_macro_hd2_control()
2439 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_compander() local
2441 ucontrol->value.integer.value[0] = rx->comp_enabled[comp]; in rx_macro_get_compander()
2451 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_set_compander() local
2453 rx->comp_enabled[comp] = value; in rx_macro_set_compander()
2463 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_mux_get() local
2466 rx->rx_port_value[widget->shift]; in rx_macro_mux_get()
2479 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_mux_put() local
2481 aif_rst = rx->rx_port_value[widget->shift]; in rx_macro_mux_put()
2490 rx->rx_port_value[widget->shift] = rx_port_value; in rx_macro_mux_put()
2494 if (rx->active_ch_cnt[aif_rst]) { in rx_macro_mux_put()
2496 &rx->active_ch_mask[aif_rst]); in rx_macro_mux_put()
2497 rx->active_ch_cnt[aif_rst]--; in rx_macro_mux_put()
2505 &rx->active_ch_mask[rx_port_value]); in rx_macro_mux_put()
2506 rx->active_ch_cnt[rx_port_value]++; in rx_macro_mux_put()
2545 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_ear_mode() local
2547 ucontrol->value.integer.value[0] = rx->is_ear_mode_on; in rx_macro_get_ear_mode()
2555 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_put_ear_mode() local
2557 rx->is_ear_mode_on = (!ucontrol->value.integer.value[0] ? false : true); in rx_macro_put_ear_mode()
2565 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_hph_hd2_mode() local
2567 ucontrol->value.integer.value[0] = rx->hph_hd2_mode; in rx_macro_get_hph_hd2_mode()
2575 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_put_hph_hd2_mode() local
2577 rx->hph_hd2_mode = ucontrol->value.integer.value[0]; in rx_macro_put_hph_hd2_mode()
2585 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_hph_pwr_mode() local
2587 ucontrol->value.enumerated.item[0] = rx->hph_pwr_mode; in rx_macro_get_hph_pwr_mode()
2595 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_put_hph_pwr_mode() local
2597 rx->hph_pwr_mode = ucontrol->value.enumerated.item[0]; in rx_macro_put_hph_pwr_mode()
2605 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_soft_clip_enable_get() local
2607 ucontrol->value.integer.value[0] = rx->is_softclip_on; in rx_macro_soft_clip_enable_get()
2616 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_soft_clip_enable_put() local
2618 rx->is_softclip_on = ucontrol->value.integer.value[0]; in rx_macro_soft_clip_enable_put()
2627 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_aux_hpf_mode_get() local
2629 ucontrol->value.integer.value[0] = rx->is_aux_hpf_on; in rx_macro_aux_hpf_mode_get()
2638 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_aux_hpf_mode_put() local
2640 rx->is_aux_hpf_on = ucontrol->value.integer.value[0]; in rx_macro_aux_hpf_mode_put()
2646 struct rx_macro *rx, in rx_macro_hphdelay_lutbypass() argument
2667 if (rx->is_ear_mode_on) in rx_macro_hphdelay_lutbypass()
2669 CDC_RX_RXn_RX_PATH_CFG1(rx, 0), in rx_macro_hphdelay_lutbypass()
2679 if (rx->hph_pwr_mode) in rx_macro_hphdelay_lutbypass()
2686 CDC_RX_RXn_RX_PATH_CFG1(rx, 0), in rx_macro_hphdelay_lutbypass()
2701 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_enable_interp_clk() local
2703 main_reg = CDC_RX_RXn_RX_PATH_CTL(rx, interp_idx); in rx_macro_enable_interp_clk()
2704 dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, interp_idx); in rx_macro_enable_interp_clk()
2705 rx_cfg2_reg = CDC_RX_RXn_RX_PATH_CFG2(rx, interp_idx); in rx_macro_enable_interp_clk()
2708 if (rx->main_clk_users[interp_idx] == 0) { in rx_macro_enable_interp_clk()
2716 rx_macro_load_compander_coeff(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2717 if (rx->hph_hd2_mode) in rx_macro_enable_interp_clk()
2719 rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2720 rx_macro_config_compander(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2722 rx_macro_config_softclip(component, rx, event); in rx_macro_enable_interp_clk()
2723 rx_macro_config_aux_hpf(component, rx, event); in rx_macro_enable_interp_clk()
2725 rx_macro_config_classh(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2727 rx->main_clk_users[interp_idx]++; in rx_macro_enable_interp_clk()
2731 rx->main_clk_users[interp_idx]--; in rx_macro_enable_interp_clk()
2732 if (rx->main_clk_users[interp_idx] <= 0) { in rx_macro_enable_interp_clk()
2733 rx->main_clk_users[interp_idx] = 0; in rx_macro_enable_interp_clk()
2753 rx_macro_config_classh(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2754 rx_macro_config_compander(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2756 rx_macro_config_softclip(component, rx, event); in rx_macro_enable_interp_clk()
2757 rx_macro_config_aux_hpf(component, rx, event); in rx_macro_enable_interp_clk()
2759 rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2760 if (rx->hph_hd2_mode) in rx_macro_enable_interp_clk()
2765 return rx->main_clk_users[interp_idx]; in rx_macro_enable_interp_clk()
2772 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_enable_mix_path() local
2775 gain_reg = CDC_RX_RXn_RX_VOL_MIX_CTL(rx, w->shift); in rx_macro_enable_mix_path()
2776 mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, w->shift); in rx_macro_enable_mix_path()
2807 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_enable_rx_path_clk() local
2812 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift), in rx_macro_enable_rx_path_clk()
2814 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CTL(rx, w->shift), in rx_macro_enable_rx_path_clk()
2818 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift), in rx_macro_enable_rx_path_clk()
3107 if (!(snd_soc_dapm_widget_name_cmp(w, "RX MIX TX0 MUX"))) in rx_macro_enable_echo()
3109 else if (!(snd_soc_dapm_widget_name_cmp(w, "RX MIX TX1 MUX"))) in rx_macro_enable_echo()
3114 if (!(snd_soc_dapm_widget_name_cmp(w, "RX MIX TX2 MUX"))) in rx_macro_enable_echo()
3134 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
3139 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
3144 SND_SOC_DAPM_AIF_IN("RX AIF1 PB", "RX_MACRO_AIF1 Playback", 0,
3147 SND_SOC_DAPM_AIF_IN("RX AIF2 PB", "RX_MACRO_AIF2 Playback", 0,
3150 SND_SOC_DAPM_AIF_IN("RX AIF3 PB", "RX_MACRO_AIF3 Playback", 0,
3153 SND_SOC_DAPM_AIF_IN("RX AIF4 PB", "RX_MACRO_AIF4 Playback", 0,
3156 SND_SOC_DAPM_AIF_OUT("RX AIF_ECHO", "RX_AIF_ECHO Capture", 0,
3188 SND_SOC_DAPM_MUX_E("RX MIX TX0 MUX", SND_SOC_NOPM,
3192 SND_SOC_DAPM_MUX_E("RX MIX TX1 MUX", SND_SOC_NOPM,
3196 SND_SOC_DAPM_MUX_E("RX MIX TX2 MUX", SND_SOC_NOPM,
3212 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
3215 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
3219 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
3223 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_AUX, 0,
3228 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp0_mux),
3229 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp1_mux),
3230 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp2_mux),
3231 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp0_mux),
3232 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp1_mux),
3233 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp2_mux),
3234 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp0_mux),
3235 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp1_mux),
3236 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp2_mux),
3238 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
3242 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
3246 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_AUX, 0,
3251 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
3253 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
3255 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
3258 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3259 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3260 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3261 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3262 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3263 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3265 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", SND_SOC_NOPM, INTERP_HPHL,
3268 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", SND_SOC_NOPM, INTERP_HPHR,
3271 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", SND_SOC_NOPM, INTERP_AUX,
3275 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3276 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3277 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3293 {"RX AIF1 PB", NULL, "RX_MCLK"},
3294 {"RX AIF2 PB", NULL, "RX_MCLK"},
3295 {"RX AIF3 PB", NULL, "RX_MCLK"},
3296 {"RX AIF4 PB", NULL, "RX_MCLK"},
3298 {"RX_MACRO RX0 MUX", "AIF1_PB", "RX AIF1 PB"},
3299 {"RX_MACRO RX1 MUX", "AIF1_PB", "RX AIF1 PB"},
3300 {"RX_MACRO RX2 MUX", "AIF1_PB", "RX AIF1 PB"},
3301 {"RX_MACRO RX3 MUX", "AIF1_PB", "RX AIF1 PB"},
3302 {"RX_MACRO RX4 MUX", "AIF1_PB", "RX AIF1 PB"},
3303 {"RX_MACRO RX5 MUX", "AIF1_PB", "RX AIF1 PB"},
3305 {"RX_MACRO RX0 MUX", "AIF2_PB", "RX AIF2 PB"},
3306 {"RX_MACRO RX1 MUX", "AIF2_PB", "RX AIF2 PB"},
3307 {"RX_MACRO RX2 MUX", "AIF2_PB", "RX AIF2 PB"},
3308 {"RX_MACRO RX3 MUX", "AIF2_PB", "RX AIF2 PB"},
3309 {"RX_MACRO RX4 MUX", "AIF2_PB", "RX AIF2 PB"},
3310 {"RX_MACRO RX5 MUX", "AIF2_PB", "RX AIF2 PB"},
3312 {"RX_MACRO RX0 MUX", "AIF3_PB", "RX AIF3 PB"},
3313 {"RX_MACRO RX1 MUX", "AIF3_PB", "RX AIF3 PB"},
3314 {"RX_MACRO RX2 MUX", "AIF3_PB", "RX AIF3 PB"},
3315 {"RX_MACRO RX3 MUX", "AIF3_PB", "RX AIF3 PB"},
3316 {"RX_MACRO RX4 MUX", "AIF3_PB", "RX AIF3 PB"},
3317 {"RX_MACRO RX5 MUX", "AIF3_PB", "RX AIF3 PB"},
3319 {"RX_MACRO RX0 MUX", "AIF4_PB", "RX AIF4 PB"},
3320 {"RX_MACRO RX1 MUX", "AIF4_PB", "RX AIF4 PB"},
3321 {"RX_MACRO RX2 MUX", "AIF4_PB", "RX AIF4 PB"},
3322 {"RX_MACRO RX3 MUX", "AIF4_PB", "RX AIF4 PB"},
3323 {"RX_MACRO RX4 MUX", "AIF4_PB", "RX AIF4 PB"},
3324 {"RX_MACRO RX5 MUX", "AIF4_PB", "RX AIF4 PB"},
3333 {"RX INT0_1 MIX1 INP0", "RX0", "RX_RX0"},
3334 {"RX INT0_1 MIX1 INP0", "RX1", "RX_RX1"},
3335 {"RX INT0_1 MIX1 INP0", "RX2", "RX_RX2"},
3336 {"RX INT0_1 MIX1 INP0", "RX3", "RX_RX3"},
3337 {"RX INT0_1 MIX1 INP0", "RX4", "RX_RX4"},
3338 {"RX INT0_1 MIX1 INP0", "RX5", "RX_RX5"},
3339 {"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"},
3340 {"RX INT0_1 MIX1 INP0", "IIR1", "IIR1"},
3341 {"RX INT0_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3342 {"RX INT0_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3343 {"RX INT0_1 MIX1 INP1", "RX0", "RX_RX0"},
3344 {"RX INT0_1 MIX1 INP1", "RX1", "RX_RX1"},
3345 {"RX INT0_1 MIX1 INP1", "RX2", "RX_RX2"},
3346 {"RX INT0_1 MIX1 INP1", "RX3", "RX_RX3"},
3347 {"RX INT0_1 MIX1 INP1", "RX4", "RX_RX4"},
3348 {"RX INT0_1 MIX1 INP1", "RX5", "RX_RX5"},
3349 {"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"},
3350 {"RX INT0_1 MIX1 INP1", "IIR1", "IIR1"},
3351 {"RX INT0_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3352 {"RX INT0_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3353 {"RX INT0_1 MIX1 INP2", "RX0", "RX_RX0"},
3354 {"RX INT0_1 MIX1 INP2", "RX1", "RX_RX1"},
3355 {"RX INT0_1 MIX1 INP2", "RX2", "RX_RX2"},
3356 {"RX INT0_1 MIX1 INP2", "RX3", "RX_RX3"},
3357 {"RX INT0_1 MIX1 INP2", "RX4", "RX_RX4"},
3358 {"RX INT0_1 MIX1 INP2", "RX5", "RX_RX5"},
3359 {"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"},
3360 {"RX INT0_1 MIX1 INP2", "IIR1", "IIR1"},
3361 {"RX INT0_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3362 {"RX INT0_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3364 {"RX INT1_1 MIX1 INP0", "RX0", "RX_RX0"},
3365 {"RX INT1_1 MIX1 INP0", "RX1", "RX_RX1"},
3366 {"RX INT1_1 MIX1 INP0", "RX2", "RX_RX2"},
3367 {"RX INT1_1 MIX1 INP0", "RX3", "RX_RX3"},
3368 {"RX INT1_1 MIX1 INP0", "RX4", "RX_RX4"},
3369 {"RX INT1_1 MIX1 INP0", "RX5", "RX_RX5"},
3370 {"RX INT1_1 MIX1 INP0", "IIR0", "IIR0"},
3371 {"RX INT1_1 MIX1 INP0", "IIR1", "IIR1"},
3372 {"RX INT1_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3373 {"RX INT1_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3374 {"RX INT1_1 MIX1 INP1", "RX0", "RX_RX0"},
3375 {"RX INT1_1 MIX1 INP1", "RX1", "RX_RX1"},
3376 {"RX INT1_1 MIX1 INP1", "RX2", "RX_RX2"},
3377 {"RX INT1_1 MIX1 INP1", "RX3", "RX_RX3"},
3378 {"RX INT1_1 MIX1 INP1", "RX4", "RX_RX4"},
3379 {"RX INT1_1 MIX1 INP1", "RX5", "RX_RX5"},
3380 {"RX INT1_1 MIX1 INP1", "IIR0", "IIR0"},
3381 {"RX INT1_1 MIX1 INP1", "IIR1", "IIR1"},
3382 {"RX INT1_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3383 {"RX INT1_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3384 {"RX INT1_1 MIX1 INP2", "RX0", "RX_RX0"},
3385 {"RX INT1_1 MIX1 INP2", "RX1", "RX_RX1"},
3386 {"RX INT1_1 MIX1 INP2", "RX2", "RX_RX2"},
3387 {"RX INT1_1 MIX1 INP2", "RX3", "RX_RX3"},
3388 {"RX INT1_1 MIX1 INP2", "RX4", "RX_RX4"},
3389 {"RX INT1_1 MIX1 INP2", "RX5", "RX_RX5"},
3390 {"RX INT1_1 MIX1 INP2", "IIR0", "IIR0"},
3391 {"RX INT1_1 MIX1 INP2", "IIR1", "IIR1"},
3392 {"RX INT1_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3393 {"RX INT1_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3395 {"RX INT2_1 MIX1 INP0", "RX0", "RX_RX0"},
3396 {"RX INT2_1 MIX1 INP0", "RX1", "RX_RX1"},
3397 {"RX INT2_1 MIX1 INP0", "RX2", "RX_RX2"},
3398 {"RX INT2_1 MIX1 INP0", "RX3", "RX_RX3"},
3399 {"RX INT2_1 MIX1 INP0", "RX4", "RX_RX4"},
3400 {"RX INT2_1 MIX1 INP0", "RX5", "RX_RX5"},
3401 {"RX INT2_1 MIX1 INP0", "IIR0", "IIR0"},
3402 {"RX INT2_1 MIX1 INP0", "IIR1", "IIR1"},
3403 {"RX INT2_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3404 {"RX INT2_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3405 {"RX INT2_1 MIX1 INP1", "RX0", "RX_RX0"},
3406 {"RX INT2_1 MIX1 INP1", "RX1", "RX_RX1"},
3407 {"RX INT2_1 MIX1 INP1", "RX2", "RX_RX2"},
3408 {"RX INT2_1 MIX1 INP1", "RX3", "RX_RX3"},
3409 {"RX INT2_1 MIX1 INP1", "RX4", "RX_RX4"},
3410 {"RX INT2_1 MIX1 INP1", "RX5", "RX_RX5"},
3411 {"RX INT2_1 MIX1 INP1", "IIR0", "IIR0"},
3412 {"RX INT2_1 MIX1 INP1", "IIR1", "IIR1"},
3413 {"RX INT2_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3414 {"RX INT2_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3415 {"RX INT2_1 MIX1 INP2", "RX0", "RX_RX0"},
3416 {"RX INT2_1 MIX1 INP2", "RX1", "RX_RX1"},
3417 {"RX INT2_1 MIX1 INP2", "RX2", "RX_RX2"},
3418 {"RX INT2_1 MIX1 INP2", "RX3", "RX_RX3"},
3419 {"RX INT2_1 MIX1 INP2", "RX4", "RX_RX4"},
3420 {"RX INT2_1 MIX1 INP2", "RX5", "RX_RX5"},
3421 {"RX INT2_1 MIX1 INP2", "IIR0", "IIR0"},
3422 {"RX INT2_1 MIX1 INP2", "IIR1", "IIR1"},
3423 {"RX INT2_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3424 {"RX INT2_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3426 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"},
3427 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"},
3428 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"},
3429 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP0"},
3430 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP1"},
3431 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP2"},
3432 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP0"},
3433 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP1"},
3434 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP2"},
3436 {"RX MIX TX0 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3437 {"RX MIX TX0 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3438 {"RX MIX TX0 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3439 {"RX MIX TX1 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3440 {"RX MIX TX1 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3441 {"RX MIX TX1 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3442 {"RX MIX TX2 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3443 {"RX MIX TX2 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3444 {"RX MIX TX2 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3445 {"RX AIF_ECHO", NULL, "RX MIX TX0 MUX"},
3446 {"RX AIF_ECHO", NULL, "RX MIX TX1 MUX"},
3447 {"RX AIF_ECHO", NULL, "RX MIX TX2 MUX"},
3448 {"RX AIF_ECHO", NULL, "RX_MCLK"},
3451 {"RX INT0_2 MUX", "RX0", "RX_RX0"},
3452 {"RX INT0_2 MUX", "RX1", "RX_RX1"},
3453 {"RX INT0_2 MUX", "RX2", "RX_RX2"},
3454 {"RX INT0_2 MUX", "RX3", "RX_RX3"},
3455 {"RX INT0_2 MUX", "RX4", "RX_RX4"},
3456 {"RX INT0_2 MUX", "RX5", "RX_RX5"},
3457 {"RX INT0_2 INTERP", NULL, "RX INT0_2 MUX"},
3458 {"RX INT0 SEC MIX", NULL, "RX INT0_2 INTERP"},
3461 {"RX INT1_2 MUX", "RX0", "RX_RX0"},
3462 {"RX INT1_2 MUX", "RX1", "RX_RX1"},
3463 {"RX INT1_2 MUX", "RX2", "RX_RX2"},
3464 {"RX INT1_2 MUX", "RX3", "RX_RX3"},
3465 {"RX INT1_2 MUX", "RX4", "RX_RX4"},
3466 {"RX INT1_2 MUX", "RX5", "RX_RX5"},
3467 {"RX INT1_2 INTERP", NULL, "RX INT1_2 MUX"},
3468 {"RX INT1 SEC MIX", NULL, "RX INT1_2 INTERP"},
3471 {"RX INT2_2 MUX", "RX0", "RX_RX0"},
3472 {"RX INT2_2 MUX", "RX1", "RX_RX1"},
3473 {"RX INT2_2 MUX", "RX2", "RX_RX2"},
3474 {"RX INT2_2 MUX", "RX3", "RX_RX3"},
3475 {"RX INT2_2 MUX", "RX4", "RX_RX4"},
3476 {"RX INT2_2 MUX", "RX5", "RX_RX5"},
3477 {"RX INT2_2 INTERP", NULL, "RX INT2_2 MUX"},
3478 {"RX INT2 SEC MIX", NULL, "RX INT2_2 INTERP"},
3480 {"RX INT0_1 INTERP", NULL, "RX INT0_1 MIX1"},
3481 {"RX INT0 SEC MIX", NULL, "RX INT0_1 INTERP"},
3482 {"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"},
3483 {"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"},
3484 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
3485 {"HPHL_OUT", NULL, "RX INT0 DEM MUX"},
3488 {"RX INT1_1 INTERP", NULL, "RX INT1_1 MIX1"},
3489 {"RX INT1 SEC MIX", NULL, "RX INT1_1 INTERP"},
3490 {"RX INT1 MIX2", NULL, "RX INT1 SEC MIX"},
3491 {"RX INT1 MIX2", NULL, "RX INT1 MIX2 INP"},
3492 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX2"},
3493 {"HPHR_OUT", NULL, "RX INT1 DEM MUX"},
3496 {"RX INT2_1 INTERP", NULL, "RX INT2_1 MIX1"},
3498 {"RX INT2 SEC MIX", NULL, "RX INT2_1 INTERP"},
3499 {"RX INT2 MIX2", NULL, "RX INT2 SEC MIX"},
3500 {"RX INT2 MIX2", NULL, "RX INT2 MIX2 INP"},
3501 {"AUX_OUT", NULL, "RX INT2 MIX2"},
3598 {"RX INT0 MIX2 INP", "SRC0", "SRC0"},
3599 {"RX INT0 MIX2 INP", "SRC1", "SRC1"},
3600 {"RX INT1 MIX2 INP", "SRC0", "SRC0"},
3601 {"RX INT1 MIX2 INP", "SRC1", "SRC1"},
3602 {"RX INT2 MIX2 INP", "SRC0", "SRC0"},
3603 {"RX INT2 MIX2 INP", "SRC1", "SRC1"},
3609 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_component_probe() local
3615 snd_soc_component_init_regmap(component, rx->regmap); in rx_macro_component_probe()
3617 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 0), in rx_macro_component_probe()
3620 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 1), in rx_macro_component_probe()
3623 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 2), in rx_macro_component_probe()
3626 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 0), in rx_macro_component_probe()
3629 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 1), in rx_macro_component_probe()
3632 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 2), in rx_macro_component_probe()
3636 switch (rx->codec_version) { in rx_macro_component_probe()
3660 rx->component = component; in rx_macro_component_probe()
3671 struct rx_macro *rx = to_rx_macro(hw); in swclk_gate_enable() local
3674 ret = clk_prepare_enable(rx->mclk); in swclk_gate_enable()
3676 dev_err(rx->dev, "unable to prepare mclk\n"); in swclk_gate_enable()
3680 rx_macro_mclk_enable(rx, true); in swclk_gate_enable()
3682 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in swclk_gate_enable()
3690 struct rx_macro *rx = to_rx_macro(hw); in swclk_gate_disable() local
3692 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in swclk_gate_disable()
3695 rx_macro_mclk_enable(rx, false); in swclk_gate_disable()
3696 clk_disable_unprepare(rx->mclk); in swclk_gate_disable()
3701 struct rx_macro *rx = to_rx_macro(hw); in swclk_gate_is_enabled() local
3704 regmap_read(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, &val); in swclk_gate_is_enabled()
3724 static int rx_macro_register_mclk_output(struct rx_macro *rx) in rx_macro_register_mclk_output() argument
3726 struct device *dev = rx->dev; in rx_macro_register_mclk_output()
3728 const char *clk_name = "lpass-rx-mclk"; in rx_macro_register_mclk_output()
3733 if (rx->npl) in rx_macro_register_mclk_output()
3734 parent_clk_name = __clk_get_name(rx->npl); in rx_macro_register_mclk_output()
3736 parent_clk_name = __clk_get_name(rx->mclk); in rx_macro_register_mclk_output()
3743 rx->hw.init = &init; in rx_macro_register_mclk_output()
3744 hw = &rx->hw; in rx_macro_register_mclk_output()
3745 ret = devm_clk_hw_register(rx->dev, hw); in rx_macro_register_mclk_output()
3753 .name = "RX-MACRO",
3767 struct rx_macro *rx; in rx_macro_probe() local
3773 rx = devm_kzalloc(dev, sizeof(*rx), GFP_KERNEL); in rx_macro_probe()
3774 if (!rx) in rx_macro_probe()
3777 rx->macro = devm_clk_get_optional(dev, "macro"); in rx_macro_probe()
3778 if (IS_ERR(rx->macro)) in rx_macro_probe()
3779 return dev_err_probe(dev, PTR_ERR(rx->macro), "unable to get macro clock\n"); in rx_macro_probe()
3781 rx->dcodec = devm_clk_get_optional(dev, "dcodec"); in rx_macro_probe()
3782 if (IS_ERR(rx->dcodec)) in rx_macro_probe()
3783 return dev_err_probe(dev, PTR_ERR(rx->dcodec), "unable to get dcodec clock\n"); in rx_macro_probe()
3785 rx->mclk = devm_clk_get(dev, "mclk"); in rx_macro_probe()
3786 if (IS_ERR(rx->mclk)) in rx_macro_probe()
3787 return dev_err_probe(dev, PTR_ERR(rx->mclk), "unable to get mclk clock\n"); in rx_macro_probe()
3790 rx->npl = devm_clk_get(dev, "npl"); in rx_macro_probe()
3791 if (IS_ERR(rx->npl)) in rx_macro_probe()
3792 return dev_err_probe(dev, PTR_ERR(rx->npl), "unable to get npl clock\n"); in rx_macro_probe()
3795 rx->fsgen = devm_clk_get(dev, "fsgen"); in rx_macro_probe()
3796 if (IS_ERR(rx->fsgen)) in rx_macro_probe()
3797 return dev_err_probe(dev, PTR_ERR(rx->fsgen), "unable to get fsgen clock\n"); in rx_macro_probe()
3799 rx->pds = lpass_macro_pds_init(dev); in rx_macro_probe()
3800 if (IS_ERR(rx->pds)) in rx_macro_probe()
3801 return PTR_ERR(rx->pds); in rx_macro_probe()
3803 ret = devm_add_action_or_reset(dev, lpass_macro_pds_exit_action, rx->pds); in rx_macro_probe()
3811 rx->codec_version = lpass_macro_get_codec_version(); in rx_macro_probe()
3814 switch (rx->codec_version) { in rx_macro_probe()
3820 rx->rxn_reg_stride = 0x80; in rx_macro_probe()
3821 rx->rxn_reg_stride2 = 0xc; in rx_macro_probe()
3834 rx->rxn_reg_stride = 0xc0; in rx_macro_probe()
3835 rx->rxn_reg_stride2 = 0x0; in rx_macro_probe()
3845 dev_err(dev, "Unsupported Codec version (%d)\n", rx->codec_version); in rx_macro_probe()
3858 rx->regmap = devm_regmap_init_mmio(dev, base, reg_config); in rx_macro_probe()
3859 if (IS_ERR(rx->regmap)) in rx_macro_probe()
3860 return PTR_ERR(rx->regmap); in rx_macro_probe()
3862 dev_set_drvdata(dev, rx); in rx_macro_probe()
3864 rx->dev = dev; in rx_macro_probe()
3867 clk_set_rate(rx->mclk, MCLK_FREQ); in rx_macro_probe()
3868 clk_set_rate(rx->npl, MCLK_FREQ); in rx_macro_probe()
3870 ret = clk_prepare_enable(rx->macro); in rx_macro_probe()
3874 ret = clk_prepare_enable(rx->dcodec); in rx_macro_probe()
3878 ret = clk_prepare_enable(rx->mclk); in rx_macro_probe()
3882 ret = clk_prepare_enable(rx->npl); in rx_macro_probe()
3886 ret = clk_prepare_enable(rx->fsgen); in rx_macro_probe()
3891 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in rx_macro_probe()
3895 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in rx_macro_probe()
3898 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in rx_macro_probe()
3914 ret = rx_macro_register_mclk_output(rx); in rx_macro_probe()
3921 clk_disable_unprepare(rx->fsgen); in rx_macro_probe()
3923 clk_disable_unprepare(rx->npl); in rx_macro_probe()
3925 clk_disable_unprepare(rx->mclk); in rx_macro_probe()
3927 clk_disable_unprepare(rx->dcodec); in rx_macro_probe()
3929 clk_disable_unprepare(rx->macro); in rx_macro_probe()
3936 struct rx_macro *rx = dev_get_drvdata(&pdev->dev); in rx_macro_remove() local
3938 clk_disable_unprepare(rx->mclk); in rx_macro_remove()
3939 clk_disable_unprepare(rx->npl); in rx_macro_remove()
3940 clk_disable_unprepare(rx->fsgen); in rx_macro_remove()
3941 clk_disable_unprepare(rx->macro); in rx_macro_remove()
3942 clk_disable_unprepare(rx->dcodec); in rx_macro_remove()
3947 .compatible = "qcom,sc7280-lpass-rx-macro",
3951 .compatible = "qcom,sm8250-lpass-rx-macro",
3954 .compatible = "qcom,sm8450-lpass-rx-macro",
3957 .compatible = "qcom,sm8550-lpass-rx-macro",
3959 .compatible = "qcom,sc8280xp-lpass-rx-macro",
3968 struct rx_macro *rx = dev_get_drvdata(dev); in rx_macro_runtime_suspend() local
3970 regcache_cache_only(rx->regmap, true); in rx_macro_runtime_suspend()
3971 regcache_mark_dirty(rx->regmap); in rx_macro_runtime_suspend()
3973 clk_disable_unprepare(rx->fsgen); in rx_macro_runtime_suspend()
3974 clk_disable_unprepare(rx->npl); in rx_macro_runtime_suspend()
3975 clk_disable_unprepare(rx->mclk); in rx_macro_runtime_suspend()
3982 struct rx_macro *rx = dev_get_drvdata(dev); in rx_macro_runtime_resume() local
3985 ret = clk_prepare_enable(rx->mclk); in rx_macro_runtime_resume()
3991 ret = clk_prepare_enable(rx->npl); in rx_macro_runtime_resume()
3997 ret = clk_prepare_enable(rx->fsgen); in rx_macro_runtime_resume()
4002 regcache_cache_only(rx->regmap, false); in rx_macro_runtime_resume()
4003 regcache_sync(rx->regmap); in rx_macro_runtime_resume()
4007 clk_disable_unprepare(rx->npl); in rx_macro_runtime_resume()
4009 clk_disable_unprepare(rx->mclk); in rx_macro_runtime_resume()
4031 MODULE_DESCRIPTION("RX macro driver");