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/linux/drivers/media/radio/wl128x/
H A Dfmdrv_rx.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * This sub-module of FM driver implements FM RX functionality.
17 fmdev->rx.rds.flag = FM_RDS_DISABLE; in fm_rx_reset_rds_cache()
18 fmdev->rx.rds.last_blk_idx = 0; in fm_rx_reset_rds_cache()
19 fmdev->rx.rds.wr_idx = 0; in fm_rx_reset_rds_cache()
20 fmdev->rx.rds.rd_idx = 0; in fm_rx_reset_rds_cache()
22 if (fmdev->rx.af_mode == FM_RX_RDS_AF_SWITCH_MODE_ON) in fm_rx_reset_rds_cache()
23 fmdev->irq_info.mask |= FM_LEV_EVENT; in fm_rx_reset_rds_cache()
28 fmdev->rx.stat_info.picode = FM_NO_PI_CODE; in fm_rx_reset_station_info()
29 fmdev->rx.stat_info.afcache_size = 0; in fm_rx_reset_station_info()
[all …]
/linux/tools/spi/
H A Dspidev_test.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Cross-compile with cross-gcc -I/path/to/cross-kernel/include
39 static uint32_t mode; variable
72 while (length- in hex_dump()
118 transfer(int fd,uint8_t const * tx,uint8_t const * rx,size_t len) transfer() argument
337 uint8_t *rx; transfer_escaped_string() local
359 uint8_t *rx; transfer_file() local
406 uint8_t *rx; transfer_buf() local
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/linux/drivers/net/ethernet/brocade/bna/
H A Dbna.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Linux network driver for QLogic BR-series Converged Network Adapter.
6 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
7 * Copyright (c) 2014-2015 QLogic Corporation
26 * input : _addr-> os dma addr in host endian format,
27 * output : _bna_dma_addr-> pointer to hw dma addr
33 (_bna_dma_addr)->msb = ((struct bna_dma_addr *)&tmp_addr)->msb; \
34 (_bna_dma_addr)->lsb = ((struct bna_dma_addr *)&tmp_addr)->lsb; \
38 * input : _bna_dma_addr-> pointer to hw dma addr
39 * output : _addr-> os dma addr in host endian format
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/linux/arch/mips/include/asm/octeon/
H A Dcvmx-spi.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
35 #include <asm/octeon/cvmx-gmxx-defs.h>
37 /* CSR typedefs have been moved to cvmx-csr-*.h */
49 int (*reset_cb) (int interface, cvmx_spi_mode_t mode);
52 int (*calendar_setup_cb) (int interface, cvmx_spi_mode_t mode,
55 /** Called for Tx and Rx clock detection */
56 int (*clock_detect_cb) (int interface, cvmx_spi_mode_t mode,
60 int (*training_cb) (int interface, cvmx_spi_mode_t mode, int timeout);
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/linux/Documentation/networking/device_drivers/can/freescale/
H A Dflexcan.rst1 .. SPDX-License-Identifier: GPL-2.0+
7 Authors: Marc Kleine-Budde <mkl@pengutronix.de>,
13 For most flexcan IP cores the driver supports 2 RX modes:
15 - FIFO
16 - mailbox
20 configured for RX-FIFO mode.
22 The RX FIFO mode uses a hardware FIFO with a depth of 6 CAN frames,
23 while the mailbox mode uses a software FIFO with a depth of up to 62
24 CAN frames. With the help of the bigger buffer, the mailbox mode
28 cores come up in a mode where RTR reception is possible.
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/linux/Documentation/userspace-api/media/cec/
H A Dcec-pin-error-inj.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
9 has low-level support for the CEC bus. Most hardware today will have
10 high-level CEC support where the hardware deals with driving the CEC bus,
19 Currently only the cec-gpio driver (when the CEC line is directly
20 connected to a pull-up GPIO line) and the AllWinner A10/A20 drm driver
25 now an ``error-inj`` file.
32 With ``cat error-inj`` you can see both the possible commands and the current
35 $ cat /sys/kernel/debug/cec/cec0/error-inj
37 # clear clear all rx and tx error injections
38 # rx-clear clear all rx error injections
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/linux/drivers/media/cec/core/
H A Dcec-pin-error-inj.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <media/cec-pin.h>
11 #include "cec-pin-priv.h"
20 { CEC_ERROR_INJ_RX_NACK_OFFSET, -1, "rx-nack" },
22 CEC_ERROR_INJ_RX_LOW_DRIVE_ARG_IDX, "rx-low-drive" },
23 { CEC_ERROR_INJ_RX_ADD_BYTE_OFFSET, -1, "rx-add-byte" },
24 { CEC_ERROR_INJ_RX_REMOVE_BYTE_OFFSET, -1, "rx-remove-byte" },
26 CEC_ERROR_INJ_RX_ARB_LOST_ARG_IDX, "rx-arb-lost" },
28 { CEC_ERROR_INJ_TX_NO_EOM_OFFSET, -1, "tx-no-eom" },
29 { CEC_ERROR_INJ_TX_EARLY_EOM_OFFSET, -1, "tx-early-eom" },
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/linux/Documentation/networking/device_drivers/ethernet/amazon/
H A Dena.rst1 .. SPDX-License-Identifier: GPL-2.0
17 The driver supports a range of ENA devices, is link-speed independent
21 Some ENA devices support SR-IOV. This driver is used for both the
22 SR-IOV Physical Function (PF) and Virtual Function (VF) devices.
25 processing by providing multiple Tx/Rx queue pairs (the maximum number
26 is advertised by the device via the Admin Queue), a dedicated MSI-X
27 interrupt vector per Tx/Rx queue pair, adaptive interrupt moderation,
31 checksum offload. Receive-side scaling (RSS) is supported for multi-core
39 Some of the ENA devices support a working mode called Low-latency
50 ena_eth_com.[ch] Tx/Rx data path.
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/linux/drivers/net/usb/
H A Dasix_common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
7 * Copyright (c) 2002-2003 TiVo Inc.
31 ret = ret < 0 ? ret : -ENODATA; in asix_read_cmd()
33 netdev_warn(dev->net, "Failed to read reg index 0x%04x: %d\n", in asix_read_cmd()
57 netdev_warn(dev->net, "Failed to write reg index 0x%04x: %d\n", in asix_write_cmd()
78 netdev_err(dev->net, "Failed to enable software MII access\n"); in asix_set_sw_mii()
88 netdev_err(dev->net, "Failed to enable hardware MII access\n"); in asix_set_hw_mii()
99 if (ret == -ENODEV || ret == -ETIMEDOUT) in asix_check_host_enable()
104 if (ret == -ENODEV) in asix_check_host_enable()
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/linux/net/ncsi/
H A Dncsi-pkt.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 unsigned char revision; /* NCSI version - 0x01 */
80 __be32 mode; /* AEN working mode */ member
88 __be32 mode; /* Link working mode */ member
89 __be32 oem_mode; /* OEM link mode */
110 unsigned char mode; /* VLAN filter mode */ member
128 __be32 mode; /* Filter mode */ member
136 __be32 mode; /* Global MC mode */ member
145 unsigned char mode; /* Flow control mode */ member
226 unsigned char vlan_mode; /* VLAN mode */
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/linux/drivers/net/hamradio/
H A Dz8530.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
43 #define RxINT_DISAB 0 /* Rx Int Disable */
44 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
45 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
56 #define RxENABLE 0x1 /* Rx Enable */
58 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
59 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
60 #define ENT_HM 0x10 /* Enter Hunt Mode */
62 #define Rx5 0x0 /* Rx 5 Bits/Character */
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/linux/Documentation/devicetree/bindings/net/
H A Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 segments of memory for buffering TX and RX, as well as the capability of
14 offloading TX/RX checksum calculation off the processor.
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
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/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-spi.c7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 #include <asm/octeon/cvmx-config.h>
36 #include <asm/octeon/cvmx-pko.h>
37 #include <asm/octeon/cvmx-spi.h>
39 #include <asm/octeon/cvmx-spxx-defs.h>
40 #include <asm/octeon/cvmx-stxx-defs.h>
41 #include <asm/octeon/cvmx-srxx-defs.h>
54 { "UNKNOWN", "TX Halfplex", "Rx Halfplex", "Duplex" };
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/linux/drivers/tty/serial/
H A Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
65 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
75 #define RxINT_DISAB 0 /* Rx Int Disable */
76 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
77 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
89 #define RxENAB 0x1 /* Rx Enable */
91 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
92 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
93 #define ENT_HM 0x10 /* Enter Hunt Mode */
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H A Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
86 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
95 #define RxINT_DISAB 0 /* Rx Int Disable */
96 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
97 #define RxINT_ALL 0x10 /* Int on all Rx Characters or error */
108 #define RxENABLE 0x1 /* Rx Enable */
110 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
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H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
57 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
67 #define RxINT_DISAB 0 /* Rx Int Disable */
68 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
69 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
81 #define RxENAB 0x1 /* Rx Enable */
83 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
84 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
85 #define ENT_HM 0x10 /* Enter Hunt Mode */
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H A Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
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/linux/include/soc/fsl/qe/
H A Ducc_slow.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
28 #define T_A 0x04000000 /* Address - the data transmitted as address
31 #define T_CM 0x02000000 /* continuous mode */
33 #define T_P 0x01000000 /* Preamble - send Preamble sequence before
54 #define R_CM 0x02000000 /* continuous mode */
57 mode */
62 #define R_NO 0x00100000 /* Rx Non Octet Aligned Packet */
74 /* Rx Data buffer must be 4 bytes aligned in most cases.*/
80 /* UCC Slow Channel Protocol Mode */
89 /* 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1) */
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H A Ducc_fast.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
39 #define R_CM_S 0x0200 /* continuous mode */
53 #define T_TM_S 0x0200 /* continuous mode */
57 /* Rx Data buffer must be 4 bytes aligned in most cases */
66 /* ucc_fast_channel_protocol_mode - UCC FAST mode */
86 /* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX */
92 /* UCC fast diagnostic mode */
100 /* UCC fast Sync length (transparent mode only) */
108 /* UCC fast RTS mode */
114 /* UCC fast receiver decoding mode */
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/linux/Documentation/networking/devlink/
H A Dmlx5.rst1 .. SPDX-License-Identifier: GPL-2.0
13 .. list-table:: Generic parameters implemented
15 * - Name
16 - Mode
17 - Validation
18 * - ``enable_roce``
19 - driverinit
20 - Type: Boolean
26 * - ``io_eq_size``
27 - driverinit
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/linux/net/tipc/
H A Dcrypto.c1 // SPDX-License-Identifier: GPL-2.0
76 STAT_BADMSGS = STAT_BADKEYS, /* rx only */
94 * struct tipc_key - TIPC keys' status indicator
97 * +-----+-----+-----+-----+-----+-----+-----+-----+
99 * +-----+-----+-----+-----+-----+-----+-----+-----+
103 #define KEY_MASK ((1 << KEY_BITS) - 1)
109 passive:2, /* rx only */
113 passive:2, /* rx only */
125 * struct tipc_tfm - TIPC TFM structure to form a list of TFMs
135 * struct tipc_aead - TIPC AEAD key structure
[all …]
/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
34 /* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */
37 /* VLAN Rx & Tx frame support. Default: disabled (cleared) */
40 /* Enable recognition of flow control frames on Rx. Default: enabled (set) */
123 /* Default TX/RX Threshold and delay timer values for SGDMA mode */
139 #define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /* First rx pkt */
140 #define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /* Last rx pkt */
148 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
153 #define XAE_RTAG_OFFSET 0x0000001C /* Rx VLAN TAG */
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/linux/drivers/net/ethernet/sun/
H A Dsungem.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */
31 #define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */
34 #define GREG_CFG_ENBUG2FIX 0x00001000 /* Fix Rx hang after overflow */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
48 #define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */
49 #define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */
50 #define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */
53 #define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
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/linux/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
221 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
222 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
265 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
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