Lines Matching +full:rx +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
35 /* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */
38 /* VLAN Rx & Tx frame support. Default: disabled (cleared) */
41 /* Enable recognition of flow control frames on Rx. Default: enabled (set) */
124 /* Default TX/RX Threshold and delay timer values for SGDMA mode */
139 #define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /* First rx pkt */
140 #define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /* Last rx pkt */
148 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
153 #define XAE_RTAG_OFFSET 0x0000001C /* Rx VLAN TAG */
160 #define XAE_RCW0_OFFSET 0x00000400 /* Rx Configuration Word 0 */
161 #define XAE_RCW1_OFFSET 0x00000404 /* Rx Configuration Word 1 */
165 #define XAE_PHYC_OFFSET 0x00000414 /* RX Max Frame Configuration */
178 #define XAE_AM0_OFFSET 0x00000750 /* Frame Filter Mask Value Bytes 3-0 */
179 #define XAE_AM1_OFFSET 0x00000754 /* Frame Filter Mask Value Bytes 7-4 */
182 #define XAE_RX_VLAN_DATA_OFFSET 0x00008000 /* RX VLAN data table address */
190 #define XAE_RAF_TXVTAGMODE_MASK 0x00000018 /* Tx VLAN TAG mode */
191 #define XAE_RAF_RXVTAGMODE_MASK 0x00000060 /* Rx VLAN TAG mode */
192 #define XAE_RAF_TXVSTRPMODE_MASK 0x00000180 /* Tx VLAN STRIP mode */
193 #define XAE_RAF_RXVSTRPMODE_MASK 0x00000600 /* Rx VLAN STRIP mode */
194 #define XAE_RAF_NEWFNCENBL_MASK 0x00000800 /* New function mode */
195 /* Extended Multicast Filtering mode */
199 #define XAE_RAF_TXVTAGMODE_SHIFT 3 /* Tx Tag mode shift bits */
200 #define XAE_RAF_RXVTAGMODE_SHIFT 5 /* Rx Tag mode shift bits */
201 #define XAE_RAF_TXVSTRPMODE_SHIFT 7 /* Tx strip mode shift bits*/
202 #define XAE_RAF_RXVSTRPMODE_SHIFT 9 /* Rx Strip mode shift bits*/
206 /* Transmit inter-frame gap adjustment value */
216 #define XAE_INT_RXCMPIT_MASK 0x00000004 /* Rx complete */
217 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
218 #define XAE_INT_RXFIFOOVR_MASK 0x00000010 /* Rx fifo overrun */
220 #define XAE_INT_RXDCMLOCK_MASK 0x00000040 /* Rx Dcm Lock */
240 /* In-Band FCS enable (FCS not stripped) */
256 /* In-Band FCS enable (FCS not generated) */
260 /* Inter-frame gap adjustment enable */
264 #define XAE_FCC_FCRX_MASK 0x20000000 /* Rx flow control enable */
269 #define XAE_EMMC_RGMII_MASK 0x20000000 /* RGMII mode enable */
270 #define XAE_EMMC_SGMII_MASK 0x10000000 /* SGMII mode enable */
271 #define XAE_EMMC_GPCS_MASK 0x08000000 /* 1000BaseX mode enable */
274 #define XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */
282 #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
327 #define XAE_FMI_PM_MASK 0x80000000 /* Promis. mode enable */
363 /* enum temac_stat - TEMAC statistics counters
419 * struct axidma_bd - Axi Dma buffer descriptor layout
455 * struct skbuf_dma_descriptor - skb for each dma descriptor
471 * struct axienet_local - axienet private per device data
478 * @switch_x_sgmii: Whether switchable 1000BaseX/SGMII mode is enabled in the core
479 * @axi_clk: AXI4-Lite bus clock
480 * @misc_clks: Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks)
486 * @napi_rx: NAPI RX control structure
491 * @rx_dma_cr: Nominal content of RX DMA control register
492 * @rx_dma_started: Set when RX DMA is started
493 * @rx_bd_v: Virtual address of the RX buffer descriptor ring
494 * @rx_bd_p: Physical address(start address) of the RX buffer descr. ring
495 * @rx_bd_num: Size of RX buffer descriptor ring
496 * @rx_bd_ci: Stores the index of the Rx buffer descriptor in the ring being
498 * @rx_packets: RX packet count for statistics
499 * @rx_bytes: RX byte count for statistics
500 * @rx_stat_sync: Synchronization object for RX stats
517 * @hw_last_counter: Last-seen value of each statistic counter
529 * @rx_irq: Axidma RX IRQ number
531 * @phy_mode: Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
538 * @rxmem: Stores rx memory size for jumbo frame handling.
541 * @rx_chan: RX DMA channel.
543 * @rx_skb_ring: Pointer to RX skb ring buffer array.
546 * @rx_ring_head: RX skb ring buffer head index.
547 * @rx_ring_tail: RX skb ring buffer tail index.
632 * struct axienet_option - Used to set axi ethernet hardware options
644 * axienet_ior - Memory mapped Axi Ethernet register read
654 return ioread32(lp->regs + offset); in axienet_ior()
664 if (lp->mii_bus) in axienet_lock_mii()
665 mutex_lock(&lp->mii_bus->mdio_lock); in axienet_lock_mii()
670 if (lp->mii_bus) in axienet_unlock_mii()
671 mutex_unlock(&lp->mii_bus->mdio_lock); in axienet_unlock_mii()
675 * axienet_iow - Memory mapped Axi Ethernet register write
686 iowrite32(value, lp->regs + offset); in axienet_iow()
690 * axienet_dma_out32 - Memory mapped Axi DMA register write.
702 iowrite32(value, lp->dma_regs + reg); in axienet_dma_out32()
707 * axienet_dma_out64 - Memory mapped Axi DMA register write.
718 iowrite64(value, lp->dma_regs + reg); in axienet_dma_out64()
724 if (lp->features & XAE_FEATURE_DMA_64BIT) in axienet_dma_out_addr()