Searched +full:rx +full:- +full:latch +full:- +full:latency +full:- +full:ns (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: SPI-NAND flash controller for MediaTek ARM SoCs10 - Chuanhong Guo <gch981213@gmail.com>13 The Mediatek SPI-NAND flash controller is an extended version of15 instructions with one continuous write and one read for up-to 0xa016 bytes. It also supports typical SPI-NAND page cache operations24 - mediatek,mt7622-snand[all …]
1 /*-4 * SPDX-License-Identifier: BSD-3-Clause72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */98 #define IGC_RXD_ERR_RXE 0x80 /* Rx Data Error */127 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */128 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */153 #define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */160 #define IGC_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */161 #define IGC_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */[all …]
2 SPDX-License-Identifier: BSD-3-Clause4 Copyright (c) 2001-2020, Intel Corporation42 * - IXGBE_ERROR_INVALID_STATE48 * - IXGBE_ERROR_POLLING53 * - IXGBE_ERROR_CAUTION58 * - IXGBE_ERROR_SOFTWARE64 * - IXGBE_ERROR_ARGUMENT69 * - IXGBE_ERROR_UNSUPPORTED162 #define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, _IDX)])419 (0x012300 + (((_i) - 24) * 4)))[all …]
2 * Copyright (c) 2017-2018 Cavium, Inc. 73 … Mask memory read Bit3 : Mask memory write Bit2 : Mask Completion Bit1 : Mask TX Bit0 : Mask RX74 … 0x00381cUL //Access:R DataWidth:0x20 // Number of RX tlp are received75 … 0x003820UL //Access:R DataWidth:0x20 // Byte number of RX are received78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…80 …R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync …81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…[all …]