Home
last modified time | relevance | path

Searched +full:rx +full:- +full:internal +full:- +full:delay (Results 1 – 25 of 296) sorted by relevance

12345678910>>...12

/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dnxp,sja1105.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Dvitesse,vsc73xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Vitesse DSA Switches were produced in the early-to-mid 2000s.
19 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
20 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
21 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
22 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
27 reside inside a SPI bus device tree node, see spi/spi-bus.txt
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Damlogic,meson-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
[all …]
H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
[all …]
H A Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
[all …]
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
[all …]
H A Drenesas,etheravb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,etheravb-r8a7742 # RZ/G1H
18 - renesas,etheravb-r8a7743 # RZ/G1M
19 - renesas,etheravb-r8a7744 # RZ/G1N
20 - renesas,etheravb-r8a7745 # RZ/G1E
[all …]
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <afd@ti.com>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
24 - $ref: ethernet-phy.yaml#
30 ti,link-loss-low:
39 ti,fiber-mode:
[all …]
H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
H A Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
[all …]
H A Drenesas,ethertsn.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Ethernet TSN End-station
10 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY.
17 - $ref: ethernet-controller.yaml#
22 - enum:
23 - renesas,r8a779g0-ethertsn # R-Car V4H
24 - const: renesas,rcar-gen4-ethertsn
[all …]
H A Dfsl,fec.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Wei Fang <wei.fang@nxp.com>
12 - NXP Linux Team <linux-imx@nxp.com>
15 - $ref: ethernet-controller.yaml#
20 - enum:
21 - fsl,imx25-fec
22 - fsl,imx27-fec
[all …]
H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwma
[all...]
H A Dallwinner,sun8i-a83t-emac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Che
[all...]
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7110-pine64-star64.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
18 starfive,tx-use-rgmii-clk;
19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
24 phy-handle = <&phy1>;
25 phy-mode = "rgmii-id";
26 starfive,tx-use-rgmii-clk;
27 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
[all …]
H A Djh7100-starfive-visionfive-v1.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7100-common.dtsi"
12 compatible = "starfive,visionfive-v1", "starfive,jh7100";
14 gpio-restart {
15 compatible = "gpio-restart";
22 phy-handle = <&phy>;
26 * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
27 * manual adjustment of the RX internal delay to work properly. The default
28 * RX delay provided by the driver (1.95ns) is too high, but applying a 50%
[all …]
H A Djh7110-milkv-mars.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
10 model = "Milk-V Mars";
15 starfive,tx-use-rgmii-clk;
16 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
17 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
29 motorcomm,tx-clk-adj-enabled;
30 motorcomm,tx-clk-10-inverted;
31 motorcomm,tx-clk-100-inverted;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
[all …]
H A Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra72-evm-revc.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
5 #include "dra72-evm-common.dtsi"
6 #include "dra72x-mmc-iodelay.dtsi"
7 #include <dt-bindings/net/ti-dp83867.h>
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
23 compatible = "shared-dma-pool";
30 compatible = "shared-dma-pool";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j721e-evm-gesi-exp-board.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
8 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/net/ti-dp83867.h>
17 #include "k3-pinctrl.h"
21 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
22 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
23 ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
24 ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dr8a779a0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3U (R8A779A0) SoC
8 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779a0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
17 /* External CAN clock - to be overridden by boards that provide it */
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/qe/
H A Ducc.txt4 - device_type : should be "network", "hldc", "uart", "transparent"
6 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8 - reg : Offset and length of the register set for the device
9 - interrupts : <a b> where a is the interrupt number and b is a
14 - pio-handle : The phandle for the Parallel I/O port configuration.
15 - port-number : for UART drivers, the port number to use, between 0 and 3.
18 CPM UART driver, the port-number is required for the QE UART driver.
19 - soft-uart : for UART drivers, if specified this means the QE UART device
20 driver should use "Soft-UART" mode, which is needed on some SOCs that have
[all …]

12345678910>>...12