Searched +full:rx +full:- +full:data +full:- +full:drv +full:- +full:microamp (Results 1 – 4 of 4) sorted by relevance
| /linux/arch/riscv/boot/dts/starfive/ |
| H A D | jh7110-starfive-visionfive-2-v1.3b.dts | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
16 starfive,tx-use-rgmii-clk;
17 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
18 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
22 starfive,tx-use-rgmii-clk;
23 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
24 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
[all …]
|
| /linux/Documentation/devicetree/bindings/net/ |
| H A D | motorcomm,yt8xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
[all …]
|
| /linux/sound/soc/codecs/ |
| H A D | rt5640.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5640.c -- RT5640/RT5639 ALSA SoC audio codec driver
27 #include <sound/soc-dapm.h>
340 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
341 static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -6562, 0);
342 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
343 static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -1762, 3000);
357 /* Interface data select */
438 SOC_ENUM("ADC IF1 Data Switch", rt5640_if1_adc_enum),
439 SOC_ENUM("DAC IF1 Data Switch", rt5640_if1_dac_enum),
[all …]
|
| /linux/drivers/net/phy/ |
| H A D | motorcomm.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: Frank <Frank.Sae@motor-comm.com>
22 * ------------------------------------------------------------
26 * ------------------------------------------------------------
28 * ------------------------------------------------------------
95 /* Rx Error Counter Register */
101 /* Extended Register's Data Register */
104 /* FIBER Auto-Negotiation link partner ability */
122 /* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */
125 /* TX Gig-E Delay is bits 7:4, default 0x5
[all …]
|