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Searched +full:rx +full:- +full:common +full:- +full:refclk +full:- +full:mode (Results 1 – 22 of 22) sorted by relevance

/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-rock-5b-pcie-srns.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * DT-overlay to run the PCIe3_4L Dual Mode controller in Root Complex
4 * mode in the SRNS (Separate Reference Clock No Spread) configuration.
7 * a setup with two ROCK 5B:s, with one board running in RC mode and the
8 * other board running in EP mode.
11 /dts-v1/;
15 rockchip,rx-common-refclk-mode = <0 0 0 0>;
H A Drk3588-rock-5b-pcie-ep.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode
7 * RC mode and the other board running in EP mode, see also the device
8 * tree overlay: rk3588-rock-5b-pcie-srns.dtso.
11 /dts-v1/;
15 rockchip,rx-common-refclk-mode = <0 0 0 0>;
23 vpcie3v3-supply = <&vcc3v3_pcie30>;
H A Drk3588-edgeble-neu6a-io.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/soc/rockchip,vop2.h>
11 stdout-path = "serial2:1500000n8";
14 hdmi1-con {
15 compatible = "hdmi-connector";
20 remote-endpoint = <&hdmi1_out_con>;
26 pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator {
27 compatible = "gated-fixed-clock";
28 #clock-cells = <0>;
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H A Drk3568-qnap-ts433.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (c) 2024 Uwe Kleine-König
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/gpio/gpio.h>
15 model = "Qnap TS-433-4G NAS System 4-Bay";
25 stdout-path = "serial2:115200n8";
29 compatible = "gpio-keys";
30 pinctrl-0 = <&copy_button_pin>, <&reset_button_pin>;
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/linux/Documentation/devicetree/bindings/phy/
H A Drockchip,pcie3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-pcie3-phy
16 - rockchip,rk3588-pcie3-phy
25 clock-names:
29 data-lanes:
32 (controller-number +1 )
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/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare USB3 Controller common properties
10 - Felipe Balbi <balbi@kernel.org>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
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/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
27 #include <dt-bindings/phy/phy.h>
33 /* TX De-emphasis parameters */
58 /* PLL Test Mode register parameters */
105 /* Refclk selection parameters */
136 /* Test Mode common reset control parameters */
184 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
198 * struct xpsgtr_phy - representation of a lane
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q-bosch-acc.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Support for the i.MX6-based Bosch ACC board.
8 * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker <matthias.winker@bosch.com>
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/leds/common.h>
20 compatible = "bosch,imx6q-acc", "fsl,imx6q";
37 backlight_lvds: backlight-lvds {
38 compatible = "pwm-backlight";
40 brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>;
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/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
40 * When accessing common PHY lane registers directly, we need to shift by 1,
41 * since the registers are 16-bit.
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f))
228 enum phy_mode mode; member
235 .mode = _mode, \
274 enum phy_mode mode; member
285 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
298 /* 40M1G25 mode init data */
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-venice-gw74xx.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include <dt-bindings/net/ti-dp83867.h>
18 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
33 stdout-path = &uart2;
42 pinctrl-names = "default";
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H A Dimx8mm-venice-gw7902.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-imx8-pcie.h>
18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
29 stdout-path = &uart2;
38 compatible = "fixed-clock";
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H A Dimx8mm-venice-gw7903.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
27 stdout-path = &uart2;
35 gpio-keys {
36 compatible = "gpio-keys";
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H A Dmba8xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
3 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/net/ti-dp83867.h>
14 compatible = "iio-hwmon";
15 io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>;
23 backlight_lvds: backlight-lvds {
24 compatible = "pwm-backlight";
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H A Dimx8mp-tqma8mpql-mba8mp-ras314.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright (c) 2023-2024 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
9 /dts-v1/;
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy-imx8-pcie.h>
14 #include <dt-bindings/pwm/pwm.h>
15 #include "imx8mp-tqma8mpql.dtsi"
18 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MP-RAS314";
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H A Dimx8mp-tqma8mpql-mba8mpxl.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2021-2022 TQ-Systems GmbH
4 * Author: Alexander Stein <alexander.stein@tq-group.com>
7 /dts-v1/;
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include "imx8mp-tqma8mpql.dtsi"
16 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL";
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/linux/drivers/net/wireless/st/cw1200/
H A Dmain.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * mac80211 glue code for mac80211 ST-Ericsson CW1200 drivers
5 * Copyright (c) 2010, ST-Ericsson
10 * Copyright (c) 2007-2009, Christian Lamparter <chunkeey@web.de>
14 * - the islsm (softmac prism54) driver, which is:
15 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
16 * - stlc45xx driver
17 * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
40 MODULE_DESCRIPTION("Softmac ST-Ericsson CW1200 common code");
58 MODULE_PARM_DESC(cw1200_power_mode, "WSM power mode. 0 == active, 1 == doze, 2 == quiescent (defau…
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/linux/sound/soc/codecs/
H A Dmadera.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // Cirrus Logic Madera class codecs common support
5 // Copyright (C) 2015-2019 Cirrus Logic, Inc. and
19 #include <linux/irqchip/irq-madera.h>
23 #include <sound/madera-pdata.h>
25 #include <dt-bindings/sound/madera.h>
144 dev_err(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
146 dev_warn(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
148 dev_dbg(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
151 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
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/linux/drivers/phy/cadence/
H A Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
189 /* PMA RX Lane registers */
225 /* PHY PCS common registers */
235 /* PHY PMA common registers */
243 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
244 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
245 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
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/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g044.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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/linux/drivers/net/ethernet/cadence/
H A Dmacb_main.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2006 Atmel Corporation
10 #include <linux/clk-provider.h>
23 #include <linux/dma-mapping.h>
37 #include <linux/firmware/xlnx-zynqmp.h>
61 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
72 …MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN -…
88 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
127 switch (bp->hw_dma_cap) { in macb_dma_desc_get_size()
152 switch (bp->hw_dma_cap) { in macb_adj_dma_desc_idx()
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/linux/drivers/infiniband/hw/hfi1/
H A Dpcie.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright(c) 2015 - 2019 Intel Corporation.
22 * Do all the common PCIe setup and initialization.
27 struct pci_dev *pdev = dd->pcidev; in hfi1_pcie_init()
43 dd_dev_err(dd, "pci enable failed: error %d\n", -ret); in hfi1_pcie_init()
49 dd_dev_err(dd, "pci_request_regions fails: err %d\n", -ret); in hfi1_pcie_init()
53 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in hfi1_pcie_init()
60 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in hfi1_pcie_init()
90 * fields required to re-initialize after a chip reset, or for
111 return -EINVAL; in hfi1_pcie_ddinit()
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