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/linux/Documentation/devicetree/bindings/net/
H A Dlantiq,etop-xway.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/lantiq,etop-xway.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
14 pattern: "^ethernet@[0-9a-f]+$"
17 const: lantiq,etop-xway
24 - description: TX interrupt
25 - description: RX interrupt
27 interrupt-names:
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H A Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
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/linux/Documentation/devicetree/bindings/dma/
H A Dintel,ldma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
21 - intel,lgm-dma1rx
22 - intel,lgm-dma1tx
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H A Dimg-mdc-dma.txt1 * IMG Multi-threaded DMA Controller (MDC)
4 - compatible: Must be "img,pistachio-mdc-dma".
5 - reg: Must contain the base address and length of the MDC registers.
6 - interrupts: Must contain all the per-channel DMA interrupts.
7 - clocks: Must contain an entry for each entry in clock-names.
8 See ../clock/clock-bindings.txt for details.
9 - clock-names: Must include the following entries:
10 - sys: MDC system interface clock.
11 - img,cr-periph: Must contain a phandle to the peripheral control syscon
13 - img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
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/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac1000_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
24 pr_info("dwmac1000: Master AXI performs %s burst length\n", in dwmac1000_dma_axi()
27 if (axi->axi_lpi_en) in dwmac1000_dma_axi()
29 if (axi->axi_xit_frm) in dwmac1000_dma_axi()
33 value |= (axi->axi_wr_osr_lmt & DMA_AXI_WR_OSR_LMT_MASK) << in dwmac1000_dma_axi()
37 value |= (axi->axi_rd_osr_lmt & DMA_AXI_RD_OSR_LMT_MASK) << in dwmac1000_dma_axi()
40 /* Depending on the UNDEF bit the Master AXI will perform any burst in dwmac1000_dma_axi()
41 * length according to the BLEN programmed (by default all BLEN are in dwmac1000_dma_axi()
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H A Ddwmac4_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
23 pr_info("dwmac4: Master AXI performs %s burst length\n", in dwmac4_dma_axi()
26 if (axi->axi_lpi_en) in dwmac4_dma_axi()
28 if (axi->axi_xit_frm) in dwmac4_dma_axi()
32 value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << in dwmac4_dma_axi()
36 value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << in dwmac4_dma_axi()
39 /* Depending on the UNDEF bit the Master AXI will perform any burst in dwmac4_dma_axi()
40 * length according to the BLEN programmed (by default all BLEN are in dwmac4_dma_axi()
44 switch (axi->axi_blen[i]) { in dwmac4_dma_axi()
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/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
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/linux/drivers/net/ethernet/atheros/atlx/
H A Datl1.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
4 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
5 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
8 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
82 /* Wake-On-Lan control register */
89 /* WOL Length ( 2 DWORD ) */
165 /* Rx jumbo packet threshold and rrd retirement timer */
215 /* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
265 /* Normal Interrupt mask without RX/TX enabled */
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/linux/drivers/net/ethernet/broadcom/
H A Dbcm63xx_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 /* maximum burst len for dma (4 bytes unit) */
24 * must be low enough so that a DMA transfer of above burst length can
29 * hardware maximum rx/tx packet size including FCS, max mtu is
30 * actually 2047, but if we set max rx size register to 2047 we won't
204 /* hw view of rx & tx dma ring */
208 /* allocated size (in bytes) for rx & tx dma ring */
215 /* dma channel id for rx */
218 /* number of dma desc in rx ring */
221 /* cpu view of rx dma ring */
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H A Dbcm4908_enet.h1 /* SPDX-License-Identifier: GPL-2.0-only */
59 #define ENET_DMA_CH0_CFG 0xa00 /* RX */
61 #define ENET_DMA_CH0_STATE_RAM 0xc00 /* RX */
67 #define ENET_DMA_CH_CFG_BURST_HALT 0x00000004 /* idle after finish current memory burst */
74 #define ENET_DMA_CH_CFG_MAX_BURST 0x0c /* max burst length permitted */
H A Db44.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */
18 #define B44_WKUP_LEN 0x0010UL /* Wakeup Length */
43 #define ISTAT_RX 0x00010000 /* RX Interrupt */
56 #define B44_TXBURST 0x00A0UL /* TX Max Burst Length */
57 #define B44_RXBURST 0x00A4UL /* RX Max Burst Length */
94 #define B44_DMARX_CTRL 0x0210UL /* DMA RX Control */
98 #define B44_DMARX_ADDR 0x0214UL /* DMA RX Descriptor Ring Address */
99 #define B44_DMARX_PTR 0x0218UL /* DMA RX Last Posted Descriptor */
100 #define B44_DMARX_STAT 0x021CUL /* DMA RX Current Active Desc. + Status */
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/linux/include/linux/phy/
H A Dphy-mipi-dphy.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
13 * MIPI D-PHY phy.
20 * Clock transitions and disable the Clock Lane HS-RX.
53 * Lane LP-00 Line state immediately before the HS-0 Line
86 * Time, in picoseconds, that the transmitter drives the HS-0
88 * burst.
97 * Time, in picoseconds, that the transmitter drives the HS-0
116 * of @hs_trail or @clk_trail, to the start of the LP- 11
117 * state following a HS burst.
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/linux/include/linux/iio/imu/
H A Dadis.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
28 * struct adis_timeouts - ADIS chip variant timeouts
29 * @reset_ms - Wait time after rst pin goes inactive
30 * @sw_reset_ms - Wait time after sw reset command
31 * @self_test_ms - Wai
139 u8 rx[4]; global() member
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/linux/arch/arm/boot/dts/axis/
H A Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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/linux/arch/mips/lantiq/xway/
H A Ddma.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
44 #define DMA_PCTRL_2W_BURST 0x1 /* 2 word burst length */
45 #define DMA_PCTRL_4W_BURST 0x2 /* 4 word burst length */
46 #define DMA_PCTRL_8W_BURST 0x3 /* 8 word burst length */
47 #define DMA_TX_BURST_SHIFT 4 /* tx burst shift */
48 #define DMA_RX_BURST_SHIFT 2 /* rx burst shift */
66 ltq_dma_w32(ch->nr, LTQ_DMA_CS); in ltq_dma_enable_irq()
67 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); in ltq_dma_enable_irq()
78 ltq_dma_w32(ch->nr, LTQ_DMA_CS); in ltq_dma_disable_irq()
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/linux/drivers/net/usb/
H A Dsmsc95xx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2007-2008 SMSC
20 #define TX_CMD_B_FRAME_LENGTH_ (0x000007FF) /* Frame Length (bytes) */
22 /* Rx status word */
24 #define RX_STS_FL_ (0x3FFF0000) /* Frame Length */
27 #define RX_STS_LE_ (0x00001000) /* Length Error */
38 /* SCSRs - System Control and Status Registers */
54 #define INT_STS_RX_STOP_ (0x00010000) /* RX Stopped */
59 #define INT_STS_RXDF_ (0x00000800) /* RX Dropped Frame */
77 #define HW_CFG_RXDOFF_ (0x00000600) /* RX Data Offset */
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/linux/drivers/net/ethernet/sun/
H A Dsunqe.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE 0x0cUL /* Local-memory Size */
45 /* The following registers are for per-qe channel information/status. */
48 #define CREG_RXDS 0x08UL /* RX descriptor ring ptr */
50 #define CREG_RIMASK 0x10UL /* RX Interrupt Mask */
54 #define CREG_RXWBUFPTR 0x20UL /* Local memory rx write ptr */
55 #define CREG_RXRBUFPTR 0x24UL /* Local memory rx read ptr */
59 #define CREG_PIPG 0x34UL /* Inter-Frame Gap */
74 #define CREG_STAT_CCOFLOW 0x00100000 /* TX Coll-counter Overflow */
79 #define CREG_STAT_RCCOFLOW 0x00001000 /* RX Coll-counter Overflow */
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H A Dsungem.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */
29 #define GREG_CFG_IBURST 0x00000001 /* Infinite Burst */
31 #define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */
33 * after infinite burst (Apple) */
34 #define GREG_CFG_ENBUG2FIX 0x00001000 /* Fix Rx hang after overflow */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
48 #define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */
49 #define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */
50 #define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */
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/linux/drivers/crypto/gemini/
H A Dsl3516-ce.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sl3516-ce.h - hardware cryptographic offloader for cortina/gemini SoC
14 * It acts the same as a network hw, with both RX and TX chained descriptors.
70 /* the burst value is not documented in the datasheet */
78 /* the burst value is not documented in the datasheet */
90 * struct sl3516_ce_descriptor - descriptor for CE operations
100 * struct desc_frame_ctrl - Information for the current descriptor
125 * struct desc_flag_status - flag for this descriptor
140 * struct desc_next - describe chaining of descriptors
158 * struct control - The value of this register is used to set the
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/linux/drivers/dma/dw-edma/
H A Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
17 #include <linux/dma-mapping.h>
19 #include "dw-edma-core.h"
20 #include "dw-edma-v0-core.h"
21 #include "dw-hdma-v0-core.h"
23 #include "../virt-dma.h"
28 return &dchan->dev->device; in dchan2dev()
34 return &chan->vc.chan.dev->device; in chan2dev()
46 struct dw_edma_chip *chip = chan->dw->chip; in dw_edma_get_pci_address()
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/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2x00queue.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
41 * @QID_RX: RX queue
62 * @SKBDESC_DMA_MAPPED_RX: &skb_dma field has been mapped for RX
86 * @desc_len: Length of the frame descriptor.
91 * of the scope of the skb->data pointer.
93 * @skb_dma: (PCI-only) the DMA address associated with the sk buffer.
112 * get_skb_frame_desc - Obtain the rt2x00 frame descriptor from a sk_buff.
119 return (struct skb_frame_desc *)&IEEE80211_SKB_CB(skb)->driver_data; in get_skb_frame_desc()
131 * @RXDONE_L2PAD: 802.11 payload has been padded to 4-byte boundary.
[all …]
/linux/drivers/usb/mtu3/
H A Dmtu3_gadget.c1 // SPDX-License-Identifier: GPL-2.0
3 * mtu3_gadget.c - MediaTek usb3 DRD peripheral support
16 __releases(mep->mtu->lock) in mtu3_req_complete()
17 __acquires(mep->mtu->lock) in mtu3_req_complete()
20 struct mtu3 *mtu = mreq->mtu; in mtu3_req_complete()
22 list_del(&mreq->lis in mtu3_req_complete()
66 u32 burst = 0; mtu3_ep_enable() local
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/linux/drivers/atm/
H A Dfore200e.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 /* rx buffer sizes */
13 #define RBD_BLK_SIZE 32 /* nbr of supplied rx buffers per rbd */
52 #define RSD_REQUIRED (((MAX_PDU_SIZE - SMALL_BUFFER_SIZE + LARGE_BUFFER_SIZE) / LARGE_BUFFER_SIZE)…
56 /* RSD_REQUIRED receive segment descriptors are enough to describe a max-sized PDU,
61 #define RSD_EXTENSION ((RSD_REQUIRED - RSD_FIXED) + 1)
65 #define FORE200E_DEV(d) ((struct fore200e*)((d)->dev_data))
66 #define FORE200E_VCC(d) ((struct fore200e_vcc*)((d)->dev_data))
113 u32 length : 16, /* total PDU length */
136 u32 length; /* number of bytes in buffer */ member
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/linux/Documentation/netlink/specs/
H A Dethtool.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
5 protocol: genetlink-legacy
8 uapi-header: linux/ethtool_netlink_generated.h
11 -
12 name: udp-tunnel-type
13 enum-name:
15 entries: [ vxlan, geneve, vxlan-gpe ]
16 enum-cnt-name: __ethtool-udp-tunnel-type-cnt
17 render-max: true
18 -
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/linux/drivers/usb/dwc3/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - DesignWare USB3 DRD Controller Core file
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
24 #include <linux/dma-mapping.h>
42 #include "../host/xhci-ext-caps.h"
47 * dwc3_get_dr_mode - Validates and sets dr_mode
53 struct device *dev = dwc->dev; in dwc3_get_dr_mode()
56 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) in dwc3_get_dr_mode()
57 dwc->dr_mode = USB_DR_MODE_OTG; in dwc3_get_dr_mode()
59 mode = dwc->dr_mode; in dwc3_get_dr_mode()
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