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Searched full:rv64i (Results 1 – 15 of 15) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
17 def WriteIDiv32 : SchedWrite; // 32-bit divide on RV64I
19 def WriteIRem32 : SchedWrite; // 32-bit remainder on RV64I
21 def WriteIMul32 : SchedWrite; // 32-bit multiply on RV64I
63 def WriteFCvtI64ToF16 : SchedWrite; // RV64I only
64 def WriteFCvtI64ToF32 : SchedWrite; // RV64I only
65 def WriteFCvtI64ToF64 : SchedWrite; // RV64I only
69 def WriteFCvtF16ToI64 : SchedWrite; // RV64I only
71 def WriteFCvtF32ToI64 : SchedWrite; // RV64I only
73 def WriteFCvtF64ToI64 : SchedWrite; // RV64I only
[all …]
H A DRISCVInstrInfoSFB.td130 // RV64I instructions
H A DRISCVInstrInfo.td748 /// RV64I instructions
1300 // ISA only read the least significant 5 bits (RV32I) or 6 bits (RV64I).
1736 // base RV32I/RV64I ISA, this lowering is only used when the A extension is
H A DRISCVISelLowering.h68 // RV64I shifts, directly matching the semantics of the named RISC-V
H A DRISCVFeatures.td1285 "RV64I Base Instruction Set">;
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dcpus.yaml152 riscv,isa-base = "rv64i";
178 riscv,isa-base = "rv64i";
199 riscv,isa-base = "rv64i";
H A Dextensions.yaml60 - rv64i
618 const: rv64i
/freebsd/sys/contrib/device-tree/src/riscv/microchip/
H A Dmpfs.dtsi26 riscv,isa-base = "rv64i";
55 riscv,isa-base = "rv64i";
86 riscv,isa-base = "rv64i";
117 riscv,isa-base = "rv64i";
148 riscv,isa-base = "rv64i";
/freebsd/sys/contrib/device-tree/src/riscv/thead/
H A Dth1520.dtsi24 riscv,isa-base = "rv64i";
48 riscv,isa-base = "rv64i";
72 riscv,isa-base = "rv64i";
96 riscv,isa-base = "rv64i";
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7100.dtsi37 riscv,isa-base = "rv64i";
66 riscv,isa-base = "rv64i";
H A Djh7110.dtsi31 riscv,isa-base = "rv64i";
60 riscv,isa-base = "rv64i";
93 riscv,isa-base = "rv64i";
126 riscv,isa-base = "rv64i";
159 riscv,isa-base = "rv64i";
/freebsd/sys/contrib/device-tree/src/riscv/renesas/
H A Dr9a07g043f.dtsi27 riscv,isa-base = "rv64i";
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h138 // RV64I inst (The base integer ISA)
H A DEmulateInstructionRISCV.cpp423 // RV32I & RV64I (The base integer ISA) //
/freebsd/sys/contrib/device-tree/src/riscv/sophgo/
H A Dcv18xx.dtsi32 riscv,isa-base = "rv64i";