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/linux/Documentation/devicetree/bindings/rtc/
H A Dmediatek,mt7622-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/rtc/mediatek,mt7622-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7622 on-SoC RTC
10 - $ref: rtc.yaml#
13 - Sean Wang <sean.wang@mediatek.com>
18 - const: mediatek,mt7622-rtc
19 - const: mediatek,soc-rtc
30 clock-names:
[all …]
H A Drtc-omap.txt4 - compatible:
5 - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
6 - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
7 This RTC IP has special WAKE-EN Register to enable
11 - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
12 - reg: Address range of rtc register set
13 - interrupts: rtc timer, alarm interrupts in order
16 - system-power-controller: whether the rtc is controlling the system power
18 - clocks: Any internal or external clocks feeding in to rtc
19 - clock-names: Corresponding names of the clocks
[all …]
H A Dmicrochip,mpfs-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/microchip,mpfs-rtc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Microchip PolarFire Soc (MPFS) RTC
11 - $ref: rtc.yaml#
14 - Daire McNamara <daire.mcnamara@microchip.com>
19 - items:
20 - const: microchip,pic64gx-rtc
21 - const: microchip,mpfs-rtc
[all …]
H A Disil,isl12057.txt1 Intersil ISL12057 I2C RTC/Alarm chip
8 ("wakeup-source") to handle the specific use-case found
9 on at least three in-tree users of the chip (NETGEAR ReadyNAS 102, 104
10 and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip
12 to the SoC but to a PMIC. It allows the device to be powered up when
13 RTC alarm rings. In order to mark the device has a wakeup source and
15 be set when the IRQ#2 pin of the chip is not connected to the SoC but
20 - "compatible": must be "isil,isl12057"
21 - "reg": I2C bus address of the device
25 - "wakeup-source": mark the chip as a wakeup source, independently of
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H A Drtc-mxc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/rtc-mxc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: rtc.yaml#
13 - Philippe Reynes <tremyfr@gmail.com>
18 - const: fsl,imx1-rtc
19 - const: fsl,imx21-rtc
20 - items:
21 - enum:
[all …]
H A Dmediatek,mt2712-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/rtc/mediatek,mt2712-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT2712 on-SoC RTC
10 - $ref: rtc.yaml#
13 - Ran Bi <ran.bi@mediatek.com>
17 const: mediatek,mt2712-rtc
26 - reg
27 - interrupts
[all …]
H A Dxlnx,zynqmp-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
11 The RTC controller has separate IRQ lines for seconds and alarm.
14 - Michal Simek <michal.simek@amd.com>
17 - $ref: rtc.yaml#
22 - const: xlnx,zynqmp-rtc
23 - items:
[all …]
H A Drenesas,sh-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/rtc/renesas,sh-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Brandt <chris.brandt@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - const: renesas,r7s72100-rtc # RZ/A1H
17 - const: renesas,sh-rtc
25 interrupt-names:
27 - const: alarm
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H A Dtrivial-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/rtc/trivial-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 This is a list of trivial RTC devices that have simple device tree
18 - $ref: rtc.yaml#
23 # AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface
24 - abracon,abb5zes3
25 # AB-RTCMC-32.768kHz-EOZ9: Real Time Clock/Calendar Module with I2C Interface
[all …]
/linux/drivers/rtc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # RTC class/drivers configuration
19 Generic RTC class support. If you say yes here, you will
26 bool "Set system time from RTC on startup and resume"
30 the value read from a specified RTC device. This is useful to avoid
34 string "RTC used to set the system time"
38 The RTC device that will be used to (re)initialize the system
44 This clock should be battery-backed, so that it reads the correct
45 time when the system boots from a power-off state. Otherwise, your
50 sleep states. Do not specify an RTC here unless it stays powered
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H A Drtc-ftrtc010.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * checkpatch fixes and usage of rtc-lib code
14 #include <linux/rtc.h>
23 #define DRV_NAME "rtc-ftrtc010"
26 MODULE_DESCRIPTION("RTC driver for Gemini SoC");
56 * Looks like the RTC in the Gemini SoC is (totaly) broken
57 * We can't read/write directly the time from RTC registers.
60 * This FIX works pretty fine and Stormlinksemi aka Cortina-Networks does
61 * the same thing, without the rtc-lib.c calls.
66 struct ftrtc010_rtc *rtc = dev_get_drvdata(dev); in ftrtc010_rtc_read_time() local
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H A Drtc-mt7622.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for MediaTek SoC based RTC
14 #include <linux/rtc.h>
49 * Ranges from 0x40 to 0x78 provide RTC time setup for year, month,
65 * The lowest value for the valid tm_year. RTC hardware would take incorrectly
72 * The most year the RTC can hold is 99 and the next to 99 in year register
84 /* Types of the function the RTC provides are time counter and alarm. */
102 struct rtc_device *rtc; member
108 static void mtk_w32(struct mtk_rtc *rtc, u32 reg, u32 val) in mtk_w32() argument
110 writel_relaxed(val, rtc->base + reg); in mtk_w32()
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H A Drtc-xgene.c1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene SoC Real Time Clock Driver
17 #include <linux/rtc.h>
20 /* RTC CSR Registers */
36 struct rtc_device *rtc; member
47 rtc_time64_to_tm(readl(pdata->csr_base + RTC_CCVR), tm); in xgene_rtc_read_time()
59 writel((u32)rtc_tm_to_time64(tm), pdata->csr_base + RTC_CLR); in xgene_rtc_set_time()
60 readl(pdata->csr_base + RTC_CLR); /* Force a barrier */ in xgene_rtc_set_time()
70 rtc_time64_to_tm(0, &alrm->time); in xgene_rtc_read_alarm()
71 alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE; in xgene_rtc_read_alarm()
[all …]
H A Drtc-jz4740.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
5 * JZ4740 SoC RTC driver
9 #include <linux/clk-provider.h>
19 #include <linux/rtc.h>
64 struct rtc_device *rtc; member
73 static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg) in jz4740_rtc_reg_read() argument
75 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
78 static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc) in jz4740_rtc_wait_write_ready() argument
82 return readl_poll_timeout(rtc->base + JZ_REG_RTC_CTRL, ctrl, in jz4740_rtc_wait_write_ready()
[all …]
H A Drtc-armada38x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * RTC driver for the Armada 38x Marvell SoCs
7 * Gregory Clement <gregory.clement@free-electrons.com>
15 #include <linux/rtc.h>
34 /* Armada38x SoC registers */
85 /* Initialize the RTC-MBUS bridge timing */
86 void (*update_mbus_timing)(struct armada38x_rtc *rtc);
87 u32 (*read_rtc_reg)(struct armada38x_rtc *rtc, u8 rtc_reg);
88 void (*clear_isr)(struct armada38x_rtc *rtc);
89 void (*unmask_interrupt)(struct armada38x_rtc *rtc);
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dnvidia,tegra-regulators-coupling.txt4 NVIDIA Tegra SoC's have a mandatory voltage-coupling between regulators.
9 ------------------------
11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
12 The CORE and RTC voltages shall be in a range of 170mV from each other
16 ------------------------
18 On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
24 - nvidia,tegra-core-regulator: Boolean property that designates regulator
26 - nvidia,tegra-rtc-regulator: Boolean property that designates regulator
27 as the "RTC domain" voltage regulator.
28 - nvidia,tegra-cpu-regulator: Boolean property that designates regulator
[all …]
/linux/Documentation/admin-guide/
H A Drtc.rst2 Real Time Clock (RTC) Drivers for Linux
8 the local time zone or daylight savings time -- unless they dual boot
9 with MS-Windows -- but will instead be set to Coordinated Universal Time
12 The newest non-PC hardware tends to just count seconds, like the time(2)
16 Linux has two largely-compatible userspace RTC API families you may
19 * /dev/rtc ... is the RTC provided by PC compatible systems,
20 so it's not very portable to non-x86 systems.
23 supported by a wide variety of RTC chips on all systems.
27 RTCs use the same API to make requests in both RTC frameworks (using
29 same functionality. For example, not every RTC is hooked up to an
[all …]
/linux/arch/arm/boot/dts/moxa/
H A Dmoxart.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* moxart.dtsi - Device Tree Include file for MOXA ART family SoC
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <0>;
28 #address-cells = <1>;
29 #size-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dsnps,archs-rtc.txt1 Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs
2 - clocksource provider for UP SoC
6 - compatible : should be "snps,archs-rtc"
7 - clocks : phandle to the source clock
11 rtc {
12 compatible = "snps,arc-rtc";
/linux/drivers/soc/tegra/
H A Dregulators-tegra20.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2019 GRATE-DRIVER project
7 * Copyright (C) 2010-2011 NVIDIA Corporation
10 #define pr_fmt(fmt) "tegra voltage-coupler: " fmt
21 #include <soc/tegra/fuse.h>
22 #include <soc/tegra/pmc.h>
53 * Tegra20 SoC has critical DVFS-capable devices that are in tegra20_core_limit()
54 * permanently-active or active at a boot time, like EMC in tegra20_core_limit()
57 * The voltage of a CORE SoC power domain shall not be dropped below in tegra20_core_limit()
60 * the state of all DVFS-critical CORE devices is synced. in tegra20_core_limit()
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dlpc1850-creg-clk.txt8 These clocks are used by the RTC and the Event Router peripherals.
13 Documentation/devicetree/bindings/clock/clock-bindings.txt
16 - compatible:
17 Should be "nxp,lpc1850-creg-clk"
18 - #clock-cells:
20 - clocks:
23 The creg-clk node must be a child of the creg syscon node.
32 soc {
34 compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
37 creg_clk: clock-controller {
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8020.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
9 #include "armada-ap806-dual.dtsi"
10 #include "armada-80x0.dtsi"
14 compatible = "marvell,armada8020", "marvell,armada-ap806-dual",
15 "marvell,armada-ap806";
18 /* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
20 * disable it. However, the RTC clock in CP slave is connected to the
/linux/Documentation/devicetree/bindings/mfd/
H A Dmediatek,mt6357.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Flora Fu <flora.fu@mediatek.com>
11 - Alexandre Mergnat <amergnat@baylibre.com>
16 USB battery charging, fuel gauge, RTC
19 - Regulator
20 - RTC
21 - Keys
26 Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5 SoC series common device tree source
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
8 * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <1>;
32 soc: soc { label
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-370-seagate-nas-xbay.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree common file for the Seagate NAS 2 and 4-bay (Armada 370 SoC).
14 #include "armada-370.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
20 stdout-path = "serial0:115200n8";
28 soc {
32 internal-regs {
38 nr-ports = <2>;
44 pinctrl-0 = <&ge0_rgmii_pins>;
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