Home
last modified time | relevance | path

Searched full:rst (Results 1 – 25 of 654) sorted by relevance

12345678910>>...27

/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Drenesas,rst.yaml4 $id: http://devicetree.org/schemas/reset/renesas,rst.yaml#
26 - renesas,r8a7742-rst # RZ/G1H
27 - renesas,r8a7743-rst # RZ/G1M
28 - renesas,r8a7744-rst # RZ/G1N
29 - renesas,r8a7745-rst # RZ/G1E
30 - renesas,r8a77470-rst # RZ/G1C
31 - renesas,r8a774a1-rst # RZ/G2M
32 - renesas,r8a774a3-rst # RZ/G2M v3.0
33 - renesas,r8a774b1-rst # RZ/G2N
34 - renesas,r8a774c0-rst # RZ/G2E
[all …]
H A Dcanaan,k210-rst.yaml4 $id: http://devicetree.org/schemas/reset/canaan,k210-rst.yaml#
19 - dt-bindings/reset/k210-rst.h
23 const: canaan,k210-rst
36 #include <dt-bindings/reset/k210-rst.h>
38 compatible = "canaan,k210-rst";
H A Daltr,rst-mgr.yaml4 $id: http://devicetree.org/schemas/reset/altr,rst-mgr.yaml#
16 const: altr,rst-mgr
19 - const: altr,stratix10-rst-mgr
20 - const: altr,rst-mgr
41 const: altr,stratix10-rst-mgr
51 compatible = "altr,rst-mgr";
H A Dreset.txt41 rst: reset-controller {
62 resets = <&rst 20>;
69 resets = <&rst 10> <&rst 11> <&rst 12> <&rst 11>;
H A Dsocfpga-reset.txt4 - compatible : "altr,rst-mgr" for (Cyclone5/Arria5/Arria10)
5 "altr,stratix10-rst-mgr","altr,rst-mgr" for Stratix10 ARM64 SoC
13 compatible = "altr,rst-mgr";
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstr64Bit.td215 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in {
225 Defs = [LR8, X2, RM], Uses = [CTR8, RM], RST = 2 in {
335 def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
336 "ldarx $RST, $addr", IIC_LdStLDARX, []>;
339 def LQARX : XForm_1_memOp<31, 276, (outs g8prc:$RST), (ins (memrr $RA, $RB):$addr),
340 "lqarx $RST, $addr", IIC_LdStLQARX, []>, isPPC64;
344 def LDARXL : XForm_1<31, 84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
345 "ldarx $RST, $addr, 1", IIC_LdStLDARX, []>, isRecordForm;
350 def LQARXL : XForm_1<31, 276, (outs g8prc:$RST), (ins (memrr $RA, $RB):$addr),
351 "lqarx $RST, $addr, 1", IIC_LdStLQARX, []>,
[all …]
H A DPPCInstrDFP.td19 defm DADD : XForm_28r<59, 2, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
20 "dadd", "$RST, $RA, $RB", IIC_FPGeneral, []>;
22 defm DADDQ : XForm_28r<63, 2, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
23 "daddq", "$RST, $RA, $RB", IIC_FPGeneral, []>;
26 defm DSUB : XForm_28r<59, 514, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
27 "dsub", "$RST, $RA, $RB", IIC_FPGeneral, []>;
29 defm DSUBQ : XForm_28r<63, 514, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
30 "dsubq", "$RST, $RA, $RB", IIC_FPGeneral, []>;
33 defm DMUL : XForm_28r<59, 34, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
34 "dmul", "$RST, $RA, $RB", IIC_FPGeneral, []>;
[all …]
H A DPPCInstrInfo.td1583 Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in {
1592 Defs = [LR, R2, RM], Uses = [CTR, RM], RST = 2 in {
1867 def LBARX : XForm_1_memOp<31, 52, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
1868 "lbarx $RST, $addr", IIC_LdStLWARX, []>,
1871 def LHARX : XForm_1_memOp<31, 116, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
1872 "lharx $RST, $addr", IIC_LdStLWARX, []>,
1875 def LWARX : XForm_1_memOp<31, 20, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
1876 "lwarx $RST, $addr", IIC_LdStLWARX, []>;
1880 def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
1881 "lbarx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm,
[all …]
H A DPPCInstrP10.td187 bits<5> RST;
201 let Inst{38-42} = RST{4-0};
261 bits<5> RST;
274 let Inst{38-42} = RST{4-0};
661 MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
663 (ins s34imm_pcrel:$D), "plbz $RST, $addr",
664 "plbz $RST, $D", IIC_LdStLFD>;
666 MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
668 (ins s34imm_pcrel:$D), "plhz $RST, $addr",
669 "plhz $RST, $D", IIC_LdStLFD>;
[all …]
H A DPPCInstrHTM.td40 let RST = 0;
45 (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB),
46 "tabortwc. $RST, $RA, $RB", IIC_SprMTSPR, []>,
50 (outs), (ins u5imm:$RST, gprc:$RA, u5imm:$RB),
51 "tabortwci. $RST, $RA, $RB", IIC_SprMTSPR, []>,
55 (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB),
56 "tabortdc. $RST, $RA, $RB", IIC_SprMTSPR, []>,
60 (outs), (ins u5imm:$RST, gprc:$RA, u5imm:$RB),
61 "tabortdci. $RST, $RA, $RB", IIC_SprMTSPR, []>,
72 let RST = 0;
[all …]
/freebsd/sys/dev/hwreset/
H A Dhwreset.c52 hwreset_assert(hwreset_t rst) in hwreset_assert() argument
55 return (HWRESET_ASSERT(rst->provider_dev, rst->rst_id, true)); in hwreset_assert()
59 hwreset_deassert(hwreset_t rst) in hwreset_deassert() argument
62 return (HWRESET_ASSERT(rst->provider_dev, rst->rst_id, false)); in hwreset_deassert()
66 hwreset_is_asserted(hwreset_t rst, bool *value) in hwreset_is_asserted() argument
69 return (HWRESET_IS_ASSERTED(rst->provider_dev, rst->rst_id, value)); in hwreset_is_asserted()
73 hwreset_release(hwreset_t rst) in hwreset_release() argument
75 free(rst, M_HWRESET); in hwreset_release()
82 hwreset_t rst; in hwreset_get_by_id() local
85 rst = malloc(sizeof(struct hwreset), M_HWRESET, in hwreset_get_by_id()
[all …]
H A Dhwreset.h50 hwreset_t *rst);
51 void hwreset_release(hwreset_t rst);
53 int hwreset_assert(hwreset_t rst);
54 int hwreset_deassert(hwreset_t rst);
55 int hwreset_is_asserted(hwreset_t rst, bool *value);
59 hwreset_t *rst);
61 hwreset_t *rst);
/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex.dtsi7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
172 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
190 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
208 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
225 resets = <&rst GPIO0_RESET>;
245 resets = <&rst GPIO1_RESET>;
266 resets = <&rst I2C0_RESET>;
277 resets = <&rst I2C1_RESET>;
288 resets = <&rst I2C2_RESET>;
299 resets = <&rst I2C3_RESET>;
[all …]
H A Dsocfpga_agilex5.dtsi7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
156 resets = <&rst I2C0_RESET>;
167 resets = <&rst I2C1_RESET>;
178 resets = <&rst I2C2_RESET>;
189 resets = <&rst I2C3_RESET>;
200 resets = <&rst I2C4_RESET>;
230 resets = <&rst GPIO1_RESET>;
300 rst: rstmgr@10d11000 { label
301 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
312 resets = <&rst SPIM0_RESET>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10.dtsi7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
177 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
195 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
213 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
230 resets = <&rst GPIO0_RESET>;
250 resets = <&rst GPIO1_RESET>;
271 resets = <&rst I2C0_RESET>;
282 resets = <&rst I2C1_RESET>;
293 resets = <&rst I2C2_RESET>;
304 resets = <&rst I2C3_RESET>;
[all …]
/freebsd/sys/dev/usb/controller/
H A Dgeneric_ehci_fdt.c71 hwreset_t rst; member
113 hwreset_t rst; in generic_ehci_fdt_attach() local
136 for (off = 0; hwreset_get_by_ofw_idx(dev, 0, off, &rst) == 0; off++) { in generic_ehci_fdt_attach()
137 err = hwreset_deassert(rst); in generic_ehci_fdt_attach()
143 rstp->rst = rst; in generic_ehci_fdt_attach()
181 struct hwrst_list *rst, *rst_tmp; in generic_ehci_fdt_detach() local
206 TAILQ_FOREACH_SAFE(rst, &sc->rst_list, next, rst_tmp) { in generic_ehci_fdt_detach()
207 hwreset_assert(rst->rst); in generic_ehci_fdt_detach()
208 hwreset_release(rst->rst); in generic_ehci_fdt_detach()
209 TAILQ_REMOVE(&sc->rst_list, rst, next); in generic_ehci_fdt_detach()
[all …]
H A Dgeneric_ohci.c73 hwreset_t rst; member
112 hwreset_t rst; in generic_ohci_attach() local
178 for (off = 0; hwreset_get_by_ofw_idx(dev, 0, off, &rst) == 0; off++) { in generic_ohci_attach()
179 err = hwreset_deassert(rst); in generic_ohci_attach()
185 rstp->rst = rst; in generic_ohci_attach()
231 struct hwrst_list *rst, *rst_tmp; in generic_ohci_detach() local
283 TAILQ_FOREACH_SAFE(rst, &sc->rst_list, next, rst_tmp) { in generic_ohci_detach()
284 hwreset_assert(rst->rst); in generic_ohci_detach()
285 hwreset_release(rst->rst); in generic_ohci_detach()
286 TAILQ_REMOVE(&sc->rst_list, rst, next); in generic_ohci_detach()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_arria10.dtsi7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
78 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
442 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
462 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
482 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
493 resets = <&rst GPIO0_RESE
782 rst: rstmgr@ffd05000 { global() label
[all...]
H A Dsocfpga.dtsi6 #include <dt-bindings/reset/altr,rst-mgr.h>
85 resets = <&rst DMA_RESET>;
103 resets = <&rst CAN0_RESET>;
112 resets = <&rst CAN1_RESET>;
529 resets = <&rst LWHPS2FPGA_RESET>;
537 resets = <&rst HPS2FPGA_RESET>;
545 resets = <&rst FPGA2HPS_RESET>;
578 resets = <&rst EMAC0_RESET>;
597 resets = <&rst EMAC1_RESET>;
613 resets = <&rst GPIO0_RESE
805 rst: rstmgr@ffd05000 { global() label
[all...]
/freebsd/contrib/tcsh/
H A Ded.init.c141 ed_Setup(int rst) in ed_Setup() argument
158 if (vdisable != (unsigned char) _POSIX_VDISABLE && rst != 0) in ed_Setup()
159 for (rst = 0; rst < C_NCC; rst++) { in ed_Setup()
160 if (ttychars[ED_IO][rst] == (unsigned char) _POSIX_VDISABLE) in ed_Setup()
161 ttychars[ED_IO][rst] = vdisable; in ed_Setup()
162 if (ttychars[EX_IO][rst] == (unsigned char) _POSIX_VDISABLE) in ed_Setup()
163 ttychars[EX_IO][rst] = vdisable; in ed_Setup()
233 if (rst) { in ed_Setup()
239 for (rst = 0; rst < C_NCC - 2; rst++) in ed_Setup()
240 if (ttychars[TS_IO][rst] != vdisable && in ed_Setup()
[all …]
/freebsd/sys/contrib/device-tree/src/mips/qca/
H A Dar9331.dtsi111 rst: reset-controller@1806001c { label
124 resets = <&rst 9>, <&rst 22>;
139 resets = <&rst 13>, <&rst 23>;
164 resets = <&rst 8>;
268 resets = <&rst 5>;
294 resets = <&rst 4>, <&rst 3>;
/freebsd/sys/contrib/dev/athk/ath10k/
H A Dahb.c186 ath10k_err(ar, "failed to get core cold rst ctrl: %ld\n", in ath10k_ahb_rst_ctrl_init()
194 ath10k_err(ar, "failed to get radio cold rst ctrl: %ld\n", in ath10k_ahb_rst_ctrl_init()
202 ath10k_err(ar, "failed to get radio warm rst ctrl: %ld\n", in ath10k_ahb_rst_ctrl_init()
210 ath10k_err(ar, "failed to get radio srif rst ctrl: %ld\n", in ath10k_ahb_rst_ctrl_init()
218 ath10k_err(ar, "failed to get cpu init rst ctrl: %ld\n", in ath10k_ahb_rst_ctrl_init()
246 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n"); in ath10k_ahb_release_reset()
252 ath10k_err(ar, "failed to deassert radio cold rst: %d\n", ret); in ath10k_ahb_release_reset()
258 ath10k_err(ar, "failed to deassert radio warm rst: %d\n", ret); in ath10k_ahb_release_reset()
264 ath10k_err(ar, "failed to deassert radio srif rst: %d\n", ret); in ath10k_ahb_release_reset()
270 ath10k_err(ar, "failed to deassert cpu init rst: %d\n", ret); in ath10k_ahb_release_reset()
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Drst3 # $File: rst,v 1.4 2023/07/27 18:26:32 christos Exp $
4 # rst: ReStructuredText http://docutils.sourceforge.net/rst.html
13 !:ext rst
/freebsd/contrib/libxo/doc/
H A DMakefile.am11 doc docs: xolint-errors.rst html
14 # The contents of xolint.rst is generated based on xolint.pl, since we
20 xolint-errors.rst: ${top_srcdir}/xolint/xolint.pl
21 perl ${top_srcdir}/xolint/xolint.pl -D > ${top_srcdir}/doc/xolint-errors.rst
/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dahci-st.txt17 - reset-names : Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst"
32 reset-names = "pwr-dwn", "sw-rst", "pwr-rst";

12345678910>>...27