Lines Matching full:rst
6 #include <dt-bindings/reset/altr,rst-mgr.h>
85 resets = <&rst DMA_RESET>;
103 resets = <&rst CAN0_RESET>;
112 resets = <&rst CAN1_RESET>;
529 resets = <&rst LWHPS2FPGA_RESET>;
537 resets = <&rst HPS2FPGA_RESET>;
545 resets = <&rst FPGA2HPS_RESET>;
578 resets = <&rst EMAC0_RESET>;
597 resets = <&rst EMAC1_RESET>;
613 resets = <&rst GPIO0_RESET>;
634 resets = <&rst GPIO1_RESET>;
655 resets = <&rst GPIO2_RESET>;
675 resets = <&rst I2C0_RESET>;
686 resets = <&rst I2C1_RESET>;
697 resets = <&rst I2C2_RESET>;
708 resets = <&rst I2C3_RESET>;
766 resets = <&rst SDMMC_RESET>;
781 resets = <&rst NAND_RESET>;
801 resets = <&rst QSPI_RESET>;
805 rst: rstmgr@ffd05000 {
807 compatible = "altr,rst-mgr";
820 resets = <&rst SDR_RESET>;
837 resets = <&rst SPIM0_RESET>;
850 resets = <&rst SPIM1_RESET>;
874 resets = <&rst SPTIMER0_RESET>;
884 resets = <&rst SPTIMER1_RESET>;
894 resets = <&rst OSC1TIMER0_RESET>;
904 resets = <&rst OSC1TIMER1_RESET>;
918 resets = <&rst UART0_RESET>;
931 resets = <&rst UART1_RESET>;
946 resets = <&rst USB0_RESET>;
959 resets = <&rst USB1_RESET>;
971 resets = <&rst L4WD0_RESET>;
980 resets = <&rst L4WD1_RESET>;