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/linux/Documentation/devicetree/bindings/serial/
H A Drs485.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/rs485.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RS485 serial communications
10 direction for the built-in half-duplex mode. The properties described
11 hereafter shall be given to a half-duplex capable UART node.
14 - Rob Herring <robh@kernel.org>
17 rs485-rts-delay:
18 description: prop-encoded-array <a b>
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-nano.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Newflow Ltd - https://www.newflow.co.uk/
5 /dts-v1/;
15 cpu0-supply = <&dcdc2_reg>;
25 compatible = "gpio-leds";
30 default-state = "off";
36 pinctrl-names = "default";
37 pinctrl-0 = <&misc_pins>;
39 misc_pins: misc-pins {
40 pinctrl-single,pins = <
[all …]
H A Dam335x-pdu001.dts6 * Copyright (C) 2018 EETS GmbH - https://www.eets.ch/
8 * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
10 * SPDX-License-Identifier: GPL-2.0+
13 /dts-v1/;
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/leds/leds-pca9532.h>
24 stdout-path = &uart3;
29 cpu0-supply = <&vdd1_reg>;
39 compatible = "regulator-fixed";
40 regulator-name = "vbat";
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-verdin-dev.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 native-hdmi-connector {
8 compatible = "hdmi-connector";
14 remote-endpoint = <&hdmi_tx_out>;
19 reg_eth2phy: regulator-eth2phy {
20 compatible = "regulator-fixed";
21 enable-active-high;
23 off-on-delay-us = <500000>;
24 regulator-max-microvolt = <3300000>;
25 regulator-min-microvolt = <3300000>;
[all …]
H A Dimx8mm-mx8menlo.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Copyright 2021-2022 Marek Vasut <marex@denx.de>
6 /dts-v1/;
8 #include "imx8mm-verdin.dtsi"
13 "toradex,verdin-imx8mm-nonwifi",
14 "toradex,verdin-imx8mm",
17 /delete-node/ gpio-keys;
20 compatible = "gpio-leds";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_led>;
[all …]
H A Dimx8mp-phyboard-pollux-rdk.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 #include <dt-bindings/leds/leds-pca9532.h>
11 #include <dt-bindings/pwm/pwm.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include "imx8mp-phycore-som.dtsi"
16 model = "PHYTEC phyBOARD-Pollux i.MX8MP";
17 compatible = "phytec,imx8mp-phyboard-pollux-rdk",
18 "phytec,imx8mp-phycore-som", "fsl,imx8mp";
[all …]
H A Dimx8mn-venice-gw7902.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
17 compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
26 stdout-path = &uart2;
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
[all …]
H A Dimx8mp-skov-reva.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 #include "imx8mp-nominal.dtsi"
6 #include <dt-bindings/leds/common.h>
27 compatible = "pwm-backlight";
28 pinctrl-0 = <&pinctrl_backlight>;
30 power-supply = <&reg_24v>;
31 enable-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
32 brightness-levels = <0 255>;
33 num-interpolated-steps = <17>;
34 default-brightness-level = <8>;
[all …]
H A Dimx8mm-venice-gw7902.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-imx8-pcie.h>
18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
29 stdout-path = &uart2;
38 compatible = "fixed-clock";
[all …]
/linux/drivers/tty/serial/8250/
H A D8250_dwlib.c1 // SPDX-License-Identifier: GPL-2.0+
17 #define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */
79 struct dw8250_port_data *d = p->private_data; in dw8250_get_divisor()
81 quot = p->uartclk / base_baud; in dw8250_get_divisor()
82 rem = p->uartclk % base_baud; in dw8250_get_divisor()
83 *frac = DIV_ROUND_CLOSEST(rem << d->dlf_size, base_baud); in dw8250_get_divisor()
98 p->status &= ~UPSTAT_AUTOCTS; in dw8250_do_set_termios()
99 if (termios->c_cflag & CRTSCTS) in dw8250_do_set_termios()
100 p->status |= UPSTAT_AUTOCTS; in dw8250_do_set_termios()
105 p->ignore_status_mask |= DW_UART_LSR_ADDR_RCVD; in dw8250_do_set_termios()
[all …]
/linux/drivers/usb/serial/
H A Dxr_serial.c1 // SPDX-License-Identifier: GPL-2.0+
10 * https://lore.kernel.org/r/20180404070634.nhspvmxcjwfgjkcv@advantechmxl-desktop
240 u8 channel; /* zero-based index or interface number */
241 struct serial_rs485 rs485; member
247 const struct xr_type *type = data->type; in xr_set_reg()
248 struct usb_serial *serial = port->serial; in xr_set_reg()
251 ret = usb_control_msg(serial->dev, usb_sndctrlpipe(serial->dev, 0), in xr_set_reg()
252 type->set_reg, in xr_set_reg()
253 USB_DIR_OUT | USB_TYPE_VENDOR | type->reg_recipient, in xr_set_reg()
257 dev_err(&port->dev, "Failed to set reg 0x%02x: %d\n", reg, ret); in xr_set_reg()
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7-mba7.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Device Tree Include file for TQ-Systems MBa7 carrier board.
5 * Copyright (C) 2016 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/net/ti-dp83867.h>
20 /delete-property/ mmc2;
26 compatible = "gpio-beeper";
31 stdout-path = &uart6;
34 gpio_buttons: gpio-keys {
[all …]
H A Dimx6qdl-mba6.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2013-2021 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
9 #include <dt-bindings/clock/imx6qdl-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/sound/fsl-imx-audmux.h>
18 /delete-property/ mmc2;
19 /delete-property/ mmc3;
24 stdout-path = &uart2;
[all …]
H A Dimx6ul-kontron-bl-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
11 gpio-leds {
12 compatible = "gpio-leds";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_gpio_leds>;
17 label = "debug-led1";
19 default-state = "off";
20 linux,default-trigger = "heartbeat";
24 label = "debug-led2";
[all …]
H A Dimx6q-bosch-acc.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Support for the i.MX6-based Bosch ACC board.
8 * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker <matthias.winker@bosch.com>
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/leds/common.h>
20 compatible = "bosch,imx6q-acc", "fsl,imx6q";
37 backlight_lvds: backlight-lvds {
38 compatible = "pwm-backlight";
40 brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>;
[all …]
/linux/drivers/tty/serial/
H A Dxilinx_uartps.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2011 - 2014 Xilinx, Inc.
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
38 /* Rx Trigger level */
41 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
43 /* Rx Timeout */
46 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
56 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
57 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
67 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
[all …]
H A Dimx.c1 // SPDX-License-Identifier: GPL-2.0+
31 #include <linux/dma-mapping.h>
34 #include <linux/dma/imx-dma.h>
126 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
155 #define UTS_LOOP (1<<12) /* Loop tx and rx */
162 /* We've been assigned a range on the "Low-density serial ports" major */
175 #define DRIVER_NAME "IMX-uart"
260 * compatible to fsl,imx6q-uart, but not fsl,imx21-uart, while the
261 * original imx6q's UART is compatible to fsl,imx21-uart. This driver
264 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_imx21_devdata, },
[all …]
H A Domap-serial.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for OMAP-UART controller.
16 * this driver as required for the omap-platform.
38 #include <linux/platform_data/serial-omap.h>
79 #define OMAP_UART_DMA_CH_FREE -1
108 * Buffer for rx dma. It is not required for tx because the buffer
118 /* timer to poll activity on rx dma */
176 offset <<= up->port.regshift; in serial_in()
177 return readw(up->port.membase + offset); in serial_in()
182 offset <<= up->port.regshift; in serial_out()
[all …]
H A Dqcom_geni_serial.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
21 #include <linux/soc/qcom/geni-se.h>
27 #include <dt-bindings/interconnect/qcom,icc.h>
175 * qcom_geni_set_rs485_mode - Set RTS pin state for RS485 mode
177 * @flag: RS485 flag to determine RTS polarity
179 * Enables manual RTS control for RS485. Sets RTS to READY or NOT_READY
180 * based on the specified flag if RS485 mode is enabled.
184 if (!(uport->rs485.flags & SER_RS485_ENABLED)) in qcom_geni_set_rs485_mode()
189 if (uport->rs485.flags & flag) in qcom_geni_set_rs485_mode()
[all …]
H A Datmel_serial.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/clk-provider.h>
24 #include <linux/dma-mapping.h>
46 * These two offsets are substracted from the RX FIFO size to define the RTS
47 * high and low thresholds
62 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
71 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
122 short pdc_rx_idx; /* current PDC RX buffer */
167 bool hd_start_rx; /* can start RX during half-duplex operation */
197 { .compatible = "atmel,at91rm9200-usart-serial" },
[all …]
H A Dsc16is7xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - common code
40 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
51 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
53 * - only on 75x/76x
56 * - only on 75x/76x
59 * - only on 75x/76x
62 * - only on 75x/76x
72 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
82 #define SC16IS7XX_IER_RDI_BIT BIT(0) /* Enable RX data interrupt */
[all …]
H A Dfsl_lpuart.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
14 #include <linux/dma-mapping.h>
30 /* All registers are 8-bit width */
119 /* 32-bit global registers only for i.MX7ULP/i.MX8x
124 /* 32-bit register definition */
241 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
246 #define DRIVER_NAME "fsl-lpuart"
349 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
350 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-edgeble-neu6a-io.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/soc/rockchip,vop2.h>
11 stdout-path = "serial2:1500000n8";
14 hdmi1-con {
15 compatible = "hdmi-connector";
20 remote-endpoint = <&hdmi1_out_con>;
26 pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator {
27 compatible = "gated-fixed-clock";
28 #clock-cells = <0>;
[all …]
/linux/Documentation/firmware-guide/acpi/
H A Denumeration.rst1 .. SPDX-License-Identifier: GPL-2.0
13 that are accessed through memory-mapped registers.
15 In order to support this and re-use the existing drivers as much as
18 - Devices that have no bus connector resource are represented as
21 - Devices behind real busses where there is a connector resource
34 This means that when ACPI_HANDLE(dev) returns non-NULL the device was
36 device-specific configuration. There is an example of this below.
43 for the device and add supported ACPI IDs. If this same IP-block is used on
44 some other non-ACPI platform, the driver might work out of the box or needs
164 FixedDMA resource array, "rx" means the second entry. The table below shows a
[all …]
/linux/include/linux/
H A Dserial_core.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
25 ((port)->cons && (port)->cons->index == (port)->line)
37 * struct uart_ops -
418 __u32 rx; global() member
593 struct serial_rs485 rs485; global() member
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