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/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom-stats.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom-stats.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. (QTI) Stats
10 - Maulik Shah <quic_mkshah@quicinc.com>
22 - qcom,rpmh-stats
23 - qcom,sdm845-rpmh-stats
24 - qcom,rpm-stats
25 # For older RPM firmware versions with fixed offset for the sleep stats
[all …]
H A Dqcom,rpm-master-stats.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpm-master-stats.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. (QTI) RPM Master Stats
10 - Konrad Dybcio <konradybcio@kernel.org>
13 The Qualcomm RPM (Resource Power Manager) architecture includes a concept
14 of "RPM Masters". They can be thought of as "the local gang leaders", usually
15 spanning a single subsystem (e.g. APSS, ADSP, CDSP). All of the RPM decisions
16 (particularly around entering hardware-driven low power modes: XO shutdown
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dlmac_common.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell CN10K RPM driver
14 * struct lmac - per lmac locks and properties
52 /* CGX & RPM has different feature set
60 * RPM DMAC_CTL0 0x4ff8
64 * defined hence CGX uses OVERFLOW bit in CMR_INT. RPM block supports
70 /* lmac offset is different is RPM */
76 /* RPM & CGX differs in number of Receive/transmit stats */
84 /* Incase of RPM get number of lmacs from RPMX_CMR_RX_LMACS[LMAC_EXIST]
92 /* Register Stats related functions */
[all …]
H A Drpm.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell CN10K RPM driver
86 /* FEC stats */
H A Dcgx.c1 // SPDX-License-Identifier: GPL-2.0
24 #define DRV_NAME "Marvell-CGX/RPM"
25 #define DRV_STRING "Marvell CGX/RPM Driver"
80 return (cgx->pdev->device == PCI_DEVID_CN10K_RPM) || in is_dev_rpm()
81 (cgx->pdev->device == PCI_DEVID_CN10KB_RPM); in is_dev_rpm()
86 if (!cgx || lmac_id < 0 || lmac_id >= cgx->max_lmac_per_mac) in is_lmac_valid()
88 return test_bit(lmac_id, &cgx->lmac_bmap); in is_lmac_valid()
98 for_each_set_bit(tmp, &cgx->lmac_bmap, cgx->max_lmac_per_mac) { in get_sequence_id_of_lmac()
112 return ((struct cgx *)cgxd)->mac_ops; in get_mac_ops()
117 return ((struct cgx *)cgxd)->fifo_len; in cgx_get_fifo_len()
[all …]
H A Drvu_cgx.c1 // SPDX-License-Identifier: GPL-2.0
31 &rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \
35 req->hdr.sig = OTX2_MBOX_REQ_SIG; \
36 req->hdr.id = _id; \
37 trace_otx2_msg_alloc(rvu->pdev, _id, sizeof(*req)); \
52 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); in is_mac_feature_supported()
58 #define CGX_OFFSET(x) ((x) * rvu->hw->lmac_per_cgx)
62 return rvu->cgxlmac2pf_map[CGX_OFFSET(cgx_id) + lmac_id]; in cgxlmac_to_pfmap()
73 return -ENODEV; in cgxlmac_to_pf()
76 rvu->cgx_cnt_max * rvu->hw->lmac_per_cgx); in cgxlmac_to_pf()
[all …]
H A Drvu_nix.c1 // SPDX-License-Identifier: GPL-2.0
97 return rvu->nix_blkaddr[blkaddr]; in rvu_get_next_nix_blkaddr()
100 if (rvu->nix_blkaddr[i] == blkaddr) in rvu_get_next_nix_blkaddr()
101 return rvu->nix_blkaddr[i + 1]; in rvu_get_next_nix_blkaddr()
114 if (!pfvf->nixlf || blkaddr < 0) in is_nixlf_attached()
126 block = &rvu->hw->block[blkaddr]; in rvu_get_nixlf_count()
127 max += block->lf.max; in rvu_get_nixlf_count()
136 struct rvu_hwinfo *hw = rvu->hw; in nix_get_nixlf()
140 if (!pfvf->nixlf || blkaddr < 0) in nix_get_nixlf()
143 *nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); in nix_get_nixlf()
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,rpm-proc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,rpm-proc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Resource Power Manager (RPM) Processor/Subsystem
10 - Bjorn Andersson <andersson@kernel.org>
11 - Konrad Dybcio <konradybcio@kernel.org>
12 - Stephan Gerhold <stephan@gerhold.net>
15 Resource Power Manager (RPM) subsystem found in various Qualcomm platforms:
17 +--------------------------------------------+
[all …]
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_pm.c1 // SPDX-License-Identifier: MIT
30 int count = atomic_read(&gt->user_wakeref); in user_forcewake()
39 GEM_BUG_ON(count > atomic_read(&gt->wakeref.count)); in user_forcewake()
40 atomic_sub(count, &gt->wakeref.count); in user_forcewake()
42 atomic_add(count, &gt->wakeref.count); in user_forcewake()
50 write_seqcount_begin(&gt->stats.lock); in runtime_begin()
51 gt->stats.start = ktime_get(); in runtime_begin()
52 gt->stats.active = true; in runtime_begin()
53 write_seqcount_end(&gt->stats.lock); in runtime_begin()
60 write_seqcount_begin(&gt->stats.lock); in runtime_end()
[all …]
H A Dintel_rps.c1 // SPDX-License-Identifier: MIT
43 return rps_to_gt(rps)->i915; in rps_to_i915()
48 return rps_to_gt(rps)->uncore; in rps_to_uncore()
55 return &gt_to_guc(gt)->slpc; in rps_to_slpc()
62 return intel_uc_uses_guc_slpc(&gt->uc); in rps_uses_slpc()
67 return mask & ~rps->pm_intrmsk_mbz; in rps_pm_sanitize_mask()
90 last = engine->stats.rps; in rps_timer()
91 engine->stats.rps = dt; in rps_timer()
99 last = rps->pm_timestamp; in rps_timer()
100 rps->pm_timestamp = timestamp; in rps_timer()
[all …]
/linux/tools/perf/Documentation/
H A Dsecurity.txt6 https://www.kernel.org/doc/html/latest/admin-guide/perf-security.html
15 1. Download selinux-policy SRPM package (e.g. selinux-policy-3.14.4-48.fc31.src.rpm on FC31)
18 # rpm -Uhv selinux-policy-3.14.4-48.fc31.src.rpm
22 # rpmbuild -bp selinux-policy.spec
24 3. Place patch below at rpmbuild/BUILD/selinux-policy-b86eaaf4dbcf2d51dd4432df7185c0eaf3cbcc02
27 # patch -p1 < selinux-policy-perf-events-perfmon.patch
30 # cat selinux-policy-perf-events-perfmon.patch
31 diff -Nura a/policy/flask/access_vectors b/policy/flask/access_vectors
32 --- a/policy/flask/access_vectors 2020-02-04 18:19:53.000000000 +0300
33 +++ b/policy/flask/access_vectors 2020-02-28 23:37:25.000000000 +0300
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8226.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
10 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
15 #include <dt-bindings/thermal/thermal.h>
[all …]
H A Dqcom-apq8084.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
6 #include <dt-bindings/gpio/gpio.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
13 interrupt-parent = <&intc>;
15 reserved-memory {
16 #address-cells = <1>;
[all …]
H A Dqcom-msm8974.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
[all …]
/linux/drivers/gpu/drm/panthor/
H A Dpanthor_device.h1 /* SPDX-License-Identifier: GPL-2.0 or MIT */
10 #include <linux/io-pgtable.h>
35 * enum panthor_device_pm_state - PM state
52 * struct panthor_irq - IRQ data
71 * enum panthor_device_profiling_mode - Profiling state
90 * struct panthor_device - Panthor device
200 /** @profile_mask: User-set profiling flags for job accounting. */
216 * struct panthor_file - Panthor file
228 /** @stats: cycle and timestamp measures for job execution. */
229 struct panthor_gpu_usage stats; member
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dqcm2290.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
10 #include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interconnect/qcom,qcm2290.h>
[all …]
H A Dmsm8998.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/firmware/qcom,scm.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/gpio/gpio.h>
14 interrupt-parent = <&intc>;
[all …]
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_log.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2014-2019 Intel Corporation
66 log->sizes[i].bytes = sections[i].default_val; in _guc_log_init_sizes()
69 if (log->sizes[GUC_LOG_SECTIONS_DEBUG].bytes >= SZ_1M && in _guc_log_init_sizes()
71 log->sizes[GUC_LOG_SECTIONS_CRASH].bytes = SZ_1M; in _guc_log_init_sizes()
76 if ((log->sizes[i].bytes % SZ_1M) == 0) { in _guc_log_init_sizes()
77 log->sizes[i].units = SZ_1M; in _guc_log_init_sizes()
78 log->sizes[i].flag = sections[i].flag; in _guc_log_init_sizes()
80 log->sizes[i].units = SZ_4K; in _guc_log_init_sizes()
81 log->sizes[i].flag = 0; in _guc_log_init_sizes()
[all …]
H A Dintel_guc_submission.c1 // SPDX-License-Identifier: MIT
39 * DOC: GuC-based command submission
42 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
50 * Covered in detail in other sections but CTBs (Host to GuC - H2G, GuC to Host
51 * - G2H) are a message interface between the i915 and GuC.
73 * with the GuC takes a non-zero amount of time we delay the disabling of
102 * sched_engine->lock
108 * guc->submission_state.lock
112 * ce->guc_state.lock
113 * Protects everything under ce->guc_state. Ensures that a context is in the
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Dkgd_pp_interface.h167 PP_SMC_POWER_PROFILE_UNKNOWN = -1,
237 * APU power is managed to system-level requirements through the PPT
247 * enum pp_power_limit_level - Used to query the power limits
255 PP_PWR_LIMIT_MIN = -1,
262 * enum pp_power_type - Used to specify the type of the requested power
275 XGMI_PLPD_NONE = -1,
283 PP_PM_POLICY_NONE = -1,
410 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
411 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
768 /* Energy (15.259uJ (2^-16) units) */
[all …]
/linux/drivers/net/ethernet/intel/igc/
H A Digc_main.c1 // SPDX-License-Identifier: GPL-2.0
33 static int debug = -1;
81 struct net_device *dev = adapter->netdev; in igc_reset()
82 struct igc_hw *hw = &adapter->hw; in igc_reset()
83 struct igc_fc_info *fc = &hw->fc; in igc_reset()
95 * - the full Rx FIFO size minus one full Tx plus one full Rx frame in igc_reset()
97 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); in igc_reset()
99 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ in igc_reset()
100 fc->low_water = fc->high_water - 16; in igc_reset()
101 fc->pause_time = 0xFFFF; in igc_reset()
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A Digb_main.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
56 "Copyright (c) 2007-2014 Intel Corporation.";
124 struct rtnl_link_stats64 *stats);
208 static int debug = -1;
253 /* igb_regdump - register printout routine */
260 switch (reginfo->ofs) { in igb_regdump()
310 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); in igb_regdump()
314 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); in igb_regdump()
315 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], in igb_regdump()
[all …]
/linux/drivers/net/ethernet/sfc/siena/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
[all …]
/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_fwif.h1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
42 /* String used in pvrdebug -h output */
44 "main,mts,cleanup,csw,bif,pm,rtd,spm,pow,hwr,hwp,rpm,dma,misc,debug"
140 /* Firmware per-DM HWR states */
155 /* DM was identified as over-running and causing HWR */
157 /* DM was innocently affected by another DM over-running which caused HWR */
270 /* Identify whether MC config is P-P or P-S */
274 /* per-os firmware shared data */
297 /* Firmware trace time-stamp field breakup */
303 /* Extra debug-info (16 bits) */
[all …]
/linux/drivers/gpu/drm/i915/
H A Di915_pmu.c2 * SPDX-License-Identifier: MIT
4 * Copyright © 2017-2018 Intel Corporation
32 static unsigned int i915_pmu_target_cpu = -1;
36 return container_of(event->pmu, struct i915_pmu, base); in event_to_pmu()
51 return engine_config_sample(event->attr.config); in engine_event_sample()
56 return (event->attr.config >> I915_PMU_CLASS_SHIFT) & 0xff; in engine_event_class()
61 return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff; in engine_event_instance()
98 return -1; in other_bit()
121 enable)) - 1); in config_mask()
125 enable)) - 1); in config_mask()
[all …]

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