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/linux/drivers/gpu/drm/omapdrm/
H A Dtcm-sita.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
26 * stride slots in a row
29 unsigned long *map, u16 stride) in free_slots() argument
33 for (i = 0; i < h; i++, pos += stride) in free_slots()
50 *pos = num_bits - w; in r2l_b2t_1d()
55 if (bit - *pos >= w) { in r2l_b2t_1d()
62 search_count = num_bits - bit + w; in r2l_b2t_1d()
63 *pos = bit - w; in r2l_b2t_1d()
66 return (area_found) ? 0 : -ENOMEM; in r2l_b2t_1d()
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/linux/Documentation/userspace-api/
H A Ddma-buf-alloc-exchange.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. Copyright 2021-2023 Collabora Ltd.
9 support for sharing pixel-buffer allocations between processes, devices, and
12 approach this sharing for two-dimensional image data.
25 Conceptually a two-dimensional array of pixels. The pixels may be stored
29 row:
30 A span along a single y-axis value, e.g. from co-ordinates (0,100) to
34 Synonym for row.
37 A span along a single x-axis value, e.g. from co-ordinates (100,0) to
41 A piece of memory for storing (parts of) pixel data. Has stride and size
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/linux/Documentation/devicetree/bindings/display/
H A Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
20 synthesis time. As a result, many of the device-tree bindings are meant to
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
32 - xylon,logicvc-3.02.a-display
33 - xylon,logicvc-4.01.a-display
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/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_frontend.h1 // SPDX-License-Identifier: GPL-2.0+
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
41 * In tiled mode, the stride is defined as the distance between the start of the
45 * Tiles are represented in row-major order, thus the end line of current tile
47 * 32-bit-aligned-width * 32 and the distance is:
48 * 32 * (32-bit-aligned-width - 31).
50 #define SUN4I_FRONTEND_LINESTRD_TILED(stride) (((stride) - 31) * 32) argument
79 #define SUN4I_FRONTEND_INSIZE(h, w) ((((h) - 1) << 16) | (((w) - 1)))
82 #define SUN4I_FRONTEND_OUTSIZE(h, w) ((((h) - 1) << 16) | (((w) - 1)))
H A Dsun4i_frontend.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
60 * The first three values of each row are coded as 13-bit signed fixed-point
62 * constant coded as a 14-bit signed fixed-point number with 4 bits for the
66 * G = 1.164 * Y - 0.39
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/linux/include/xen/interface/io/
H A Dfbif.h1 /* SPDX-License-Identifier: MIT */
3 * fbif.h -- Xen virtual frame buffer device
12 /* Out events (frontend -> backend) */
22 * Capable frontend sets feature-update in xenstore.
23 * Backend requests it by setting request-update in xenstore.
37 * Capable backend sets feature-resize in xenstore.
45 int32_t stride; /* stride in bytes */ member
59 /* In events (backend -> frontend) */
97 uint32_t line_length; /* length of a row of pixels (in bytes) */
/linux/drivers/nvmem/
H A Dbcm-ocotp.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/nvmem-provider.h>
45 #define OTPC_CMD_MASK (BIT(OTPC_COMMAND_COMMAND_WIDTH) - 1)
46 #define OTPC_ADDR_MASK (BIT(OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH) - 1)
52 /* 128 bit row / 4 words support. */
54 /* 128 bit row / 4 words support. */
114 return -EAGAIN; in poll_cpu_status()
157 u32 address = offset / priv->config->word_size; in bcm_otpc_read()
161 set_command(priv->base, OTPC_CMD_READ); in bcm_otpc_read()
162 set_cpu_address(priv->base, address++); in bcm_otpc_read()
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/linux/include/uapi/drm/
H A Ddrm_fourcc.h39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
225 * Half-Floating point - 16b/component
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H A Di915_drm.h19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
37 * subject to backwards-compatibility constraints.
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
44 * event from the GPU L3 cache. Additional information supplied is ROW,
46 * track of these events, and if a specific cache-line seems to have a
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
66 * struct i915_user_extension - Base class for defining a chain of extensions
82 * .. code-block:: C
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/linux/drivers/gpu/drm/logicvc/
H A Dlogicvc_of.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
14 { "lvds-4bits", LOGICVC_DISPLAY_INTERFACE_LVDS_4BITS },
15 { "lvds-3bits", LOGICVC_DISPLAY_INTERFACE_LVDS_3BITS },
40 .name = "xylon,display-interface",
48 .name = "xylon,display-colorspace",
56 .name = "xylon,display-depth",
60 .name = "xylon,row-stride",
67 .name = "xylon,background-layer",
71 .name = "xylon,layers-configurable",
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/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-yuv-planar.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. planar-yuv:
13 - Semi-planar formats use two planes. The first plane is the luma plane and
17 - Fully planar formats use three planes to store the Y, Cb and Cr components
21 tiled. Padding may be supported at the end of the lines, and the line stride of
22 the chroma planes may be constrained by the line stride of the luma plane.
27 and applications that support the multi-planar API, described in
28 :ref:`planar-apis`. Unless explicitly documented as supporting non-contiguous
32 Semi-Planar YUV Formats
43 subsampling, the chroma line stride (in bytes) is thus equal to twice the luma
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/linux/drivers/thermal/intel/
H A Dintel_hfi.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
22 #define pr_fmt(fmt) "intel-hfi: " fmt
33 #include <linux/percpu-defs.h>
79 * struct hfi_cpu_data - HFI capabilities per CPU
92 * struct hfi_hdr - Header of the HFI table
104 * struct hfi_instance - Representation of an HFI instance (i.e., a table)
133 * struct hfi_features - Supported HFI features
135 * @cpu_stride: Stride size to locate the capability data of a logical
136 * processor within the table (i.e., row stride)
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/linux/drivers/net/ethernet/sfc/
H A Dmae.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2020-2022 Xilinx Inc.
29 return -EINVAL; in efx_mae_allocate_mport()
31 return -EINVAL; in efx_mae_allocate_mport()
42 return -EIO; in efx_mae_allocate_mport()
64 MAE_MPORT_SELECTOR_PPORT_ID, efx->port_num); in efx_mae_mport_wire()
104 return -EIO; in efx_mae_fw_lookup_mport()
120 efx->net_dev->mtu); in efx_mae_start_counters()
129 return -EIO; in efx_mae_start_counters()
132 netif_dbg(efx, drv, efx->net_dev, in efx_mae_start_counters()
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/linux/drivers/gpu/drm/vmwgfx/
H A Dvmw_surface_cache.h1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
4 * Copyright (c) 2021-2024 Broadcom. All Rights Reserved. The term
43 return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp; in clamped_umul32()
47 * vmw_surface_get_desc - Look up the appropriate SVGA3dSurfaceDesc for the
60 * vmw_surface_get_mip_size - Given a base level size and the mip level,
80 block_size->width = __KERNEL_DIV_ROUND_UP(pixel_size->width, in vmw_surface_get_size_in_blocks()
81 desc->blockSize.width); in vmw_surface_get_size_in_blocks()
82 block_size->height = __KERNEL_DIV_ROUND_UP(pixel_size->height, in vmw_surface_get_size_in_blocks()
83 desc->blockSize.height); in vmw_surface_get_size_in_blocks()
84 block_size->depth = __KERNEL_DIV_ROUND_UP(pixel_size->depth, in vmw_surface_get_size_in_blocks()
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/linux/drivers/staging/media/ipu3/
H A Dipu3-abi.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include "include/uapi/intel-ipu3.h"
106 #define IMGU_REG_L1_PHYS (IMGU_REG_BASE + 0x304) /* 27-bit pfn */
121 /* For each definition there is signal pair : valid [bit 0]- accept [bit 1] */
151 #define IMGU_GP_STRMON_STAT_MOD_PORT_S2V(n) (1 << (((n) - 1) * 2 + 20))
154 #define IMGU_GP_STRMON_STAT_ACCS_PORT_ACC(n) (1 << (((n) - 1) * 2))
157 #define IMGU_GP_STRMON_STAT_ACCS2SP1_MON_PORT_ACC(n) (1 << (((n) - 1) * 2))
160 #define IMGU_GP_STRMON_STAT_ACCS2SP2_MON_PORT_ACC(n) (1 << (((n) - 1) * 2))
212 #define IMGU_GDC_LUT_MASK ((1 << 12) - 1) /* Range -1024..+1024 */
353 /* n = 0..IPU3_CSS_PIPE_ID_NUM-1 */
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/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da6xx.xml1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
16 <!--
19 - "cmd" - the register is used outside of renderpass and blits,
21 - "rp_blit" - the register is used inside renderpass or blits
28 -->
34 <bitfield name="CP_IPC_INTR_0" pos="4" type="boolean" variants="A7XX-"/>
35 <bitfield name="CP_IPC_INTR_1" pos="5" type="boolean" variants="A7XX-"/>
46 <!-- Same as above but different name??: -->
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H A Da4xx.xml1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
70 <!-- hmm, shifted one compared to a3xx?!? -->
88 <!-- beyond here it does not appear to be shifted -->
145 <!-- 0x00 .. 0x02 -->
147 <!-- 8-bit formats -->
154 <!-- 16-bit formats -->
157 <!-- 0x0a -->
160 <!-- 0x0c -->
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H A Da3xx.xml1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
11 <value name="TILE_4X4" value="1"/> <!-- "normal" case for textures -->
12 <value name="TILE_32X32" value="2"/> <!-- only used in GMEM -->
13 <value name="TILE_4X2" value="3"/> <!-- only used for CrCb -->
60 <!-- seems to be no NORM variants for 32bit.. -->
106 <!--
111 -->
137 <value name="TFMT_A8_UNORM" value="0x2c"/> <!-- GL_ALPHA -->
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H A Da5xx.xml1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
32 <value value="0x37" name="RB5_R10G10B10A2_UNORM"/> <!-- GL_RGB10_A2 -->
33 <value value="0x3a" name="RB5_R10G10B10A2_UINT"/> <!-- GL_RGB10_A2UI -->
34 <value value="0x42" name="RB5_R11G11B10_FLOAT"/> <!-- GL_R11F_G11F_B10F -->
251 <value value="8" name="BLIT_ZS"/> <!-- depth or combined depth+stencil -->
252 <value value="9" name="BLIT_S"/> <!-- separate stencil -->
255 <!-- see comment in a4xx.xml about script to extract countables from test-perf output -->
851 <!-- CP Interrupt bits -->
[all …]
H A Da2xx.xml1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
1032 <bitfield name="ROW" low="3" high="5" type="uint"/>
1048 <!--
1053 -->
1158 <!-- The width is uncertain -->
1216 <array offset="0x0c06" name="VSC_PIPE" stride="3" length="8">
1779 <!-- biased: 2*color-1 (range -1,1 when sampling) -->
1781 <!-- gamma: sRGB to linear - doesn't seem to work on adreno? -->
[all …]
/linux/drivers/video/fbdev/
H A Dsstfb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/video/sstfb.c -- voodoo graphics frame buffer
5 * Copyright (c) 2000-2002 Ghozlane Toumi <gtoumi@laposte.net>
16 * (enable driver on big-endian machines (hppa), ioctl fixes)
26 * add /sys/class/graphics/fbX/vgapass sysfs-interface
34 * 0x000000 - 0x3fffff : registers (4MB)
35 * 0x400000 - 0x7fffff : linear frame buffer (4MB)
36 * 0x800000 - 0xffffff : texture memory (8MB)
42 -TODO: at one time or another test that the mode is acceptable by the monitor
43 -ASK: Can I choose different ordering for the color bitfields (rgba argb ...)
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/linux/drivers/net/ethernet/mellanox/mlx5/core/en/
H A Dparams.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
26 u8 req_page_shift = xsk ? order_base_2(xsk->chunk_size) : PAGE_SHIFT; in mlx5e_mpwrq_page_shift()
29 /* Regular RQ uses order-0 pages, the NIC must be able to map them. */ in mlx5e_mpwrq_page_shift()
40 * user-mode memory. The stricter guarantees we have, the faster in mlx5e_mpwrq_umr_mode()
42 * 1. MTT - direct mapping in page granularity. in mlx5e_mpwrq_umr_mode()
43 * 2. KSM - indirect mapping to another MKey to arbitrary addresses, but in mlx5e_mpwrq_umr_mode()
45 * 3. KLM - indirect mapping to another MKey to arbitrary addresses, and in mlx5e_mpwrq_umr_mode()
49 bool unaligned = xsk ? xsk->unaligned : false; in mlx5e_mpwrq_umr_mode()
53 oversized = xsk->chunk_size < (1 << page_shift); in mlx5e_mpwrq_umr_mode()
54 WARN_ON_ONCE(xsk->chunk_size > (1 << page_shift)); in mlx5e_mpwrq_umr_mode()
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/linux/mm/
H A Dcompaction.c1 // SPDX-License-Identifier: GPL-2.0
9 * Copyright IBM Corp. 2007-2010 Mel Gorman <mel@csn.ul.ie>
17 #include <linux/backing-dev.h>
20 #include <linux/page-isolation.h>
46 * order == -1 is expected when compacting proactively via
53 return order == -1; in is_via_compact_memory()
71 * Page order with-respect-to which proactive compaction
80 #define COMPACTION_HPAGE_ORDER (PMD_SHIFT - PAGE_SHIFT)
102 list_del(&page->lru); in release_free_list()
128 zone->compact_considered = 0; in defer_compaction()
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/linux/drivers/infiniband/hw/bnxt_re/
H A Dqplib_fp.c2 * Broadcom NetXtreme-E RoCE driver.
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
66 qp->sq.condition = false; in bnxt_qplib_cancel_phantom_processing()
67 qp->sq.send_phantom = false; in bnxt_qplib_cancel_phantom_processing()
68 qp->sq.single = false; in bnxt_qplib_cancel_phantom_processing()
76 scq = qp->scq; in __bnxt_qplib_add_flush_qp()
77 rcq = qp->rcq; in __bnxt_qplib_add_flush_qp()
79 if (!qp->sq.flushed) { in __bnxt_qplib_add_flush_qp()
80 dev_dbg(&scq->hwq.pdev->dev, in __bnxt_qplib_add_flush_qp()
83 list_add_tail(&qp->sq_flush, &scq->sqf_head); in __bnxt_qplib_add_flush_qp()
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/linux/tools/include/uapi/drm/
H A Di915_drm.h19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
37 * subject to backwards-compatibility constraints.
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
44 * event from the GPU L3 cache. Additional information supplied is ROW,
46 * track of these events, and if a specific cache-line seems to have a
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
66 * struct i915_user_extension - Base class for defining a chain of extensions
82 * .. code-block:: C
[all …]

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