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/linux/Documentation/devicetree/bindings/net/
H A Dmediatek-dwmac.yaml54 - description: RMII reference clock provided by MAC
81 For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
83 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,
91 For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
93 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple
96 mediatek,rmii-rxc:
99 If present, indicates that the RMII reference clock, which is from external
102 mediatek,rmii-clk-from-mac:
105 If present, indicates that MAC provides the RMII reference clock, which
114 which is from external PHYs in RMII case, and it rarely happen.
[all …]
H A Dmicrel.txt23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
37 - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
H A Dnxp,tja11xx.yaml49 nxp,rmii-refclk-in:
53 in RMII mode. This clock signal is provided by the PHY and is
60 interface reference clock input when RMII mode enabled.
62 reference clock output when RMII mode enabled.
77 nxp,rmii-refclk-out:
79 description: Enable 50MHz RMII reference clock output on REF_CLK pin.
110 nxp,rmii-refclk-in;
H A Dactions,owl-emac.yaml14 It provides the RMII and SMII interfaces and is compliant with the
44 - const: rmii
81 clock-names = "eth", "rmii";
83 phy-mode = "rmii";
H A Dcpsw-phy-sel.txt13 -rmii-clock-ext : If present, the driver will configure the RMII
29 rmii-clock-ext;
H A Dfaraday,ftgmac100.yaml36 - description: RMII RCLK gate for AST2500/2600
47 - rmii
54 rmii (100bT) but kept as a separate property in case NC-SI grows support
H A Dmediatek,star-emac.yaml51 mediatek,rmii-rxc:
54 If present, indicates that the RMII reference clock, which is from external
97 phy-mode = "rmii";
H A Dlpc-eth.txt10 absent, "rmii" is assumed.
26 phy-mode = "rmii";
H A Ddavinci_emac.txt23 - ti,davinci-rmii-en: 1 byte, 1 means use RMII
H A Dloongson,ls1c-emac.yaml22 - RMII interface
66 - rmii
H A Dadi,adin.yaml35 When operating in RMII mode, this option configures the FIFO depth.
77 phy-mode = "rmii";
/linux/arch/powerpc/boot/dts/
H A Dkmeter1.dts346 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
358 phy-connection-type = "rmii";
362 /* Eth-1 (UCC5, MDIO 0x08, RMII) */
374 phy-connection-type = "rmii";
378 /* Eth-2 (UCC6, MDIO 0x09, RMII) */
390 phy-connection-type = "rmii";
394 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
406 phy-connection-type = "rmii";
410 /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
422 phy-connection-type = "rmii";
[all …]
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmicrochip,ksz.yaml71 MII / RMII (except TX_CLK/REFCLKI, COL and CRS) and CLKO_25_125 lines.
126 microchip,rmii-clk-internal:
130 can select between internal and external RMII reference
132 the RMII of ksz88x3 is provided by the ksz88x3 internally
136 If microchip,rmii-clk-internal is set, ksz88x3 will provide
137 rmii reference clock internally, otherwise reference clock
140 microchip,rmii-clk-internal: [ethernet]
H A Dlan9303.txt31 fixed-link { /* RMII fixed link to LAN9303 */
47 port@0 { /* RMII fixed link to master */
/linux/drivers/pinctrl/qcom/
H A Dpinctrl-ipq4019.c509 QCA_PIN_FUNCTION(rmii),
587 PINGROUP(36, rmii, led2, led0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
589 PINGROUP(37, rmii, wifi0, wifi1, led1, NA, NA, NA, NA, NA, NA, NA, NA,
591 PINGROUP(38, rmii, led2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
593 PINGROUP(39, rmii, pcie, led3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
595 PINGROUP(40, rmii, wifi0, wifi1, smart2, led4, NA, NA, NA, NA, NA, NA,
597 PINGROUP(41, rmii, wifi0, wifi1, smart2, NA, NA, NA, NA, NA, NA, NA,
599 PINGROUP(42, rmii, wifi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
601 PINGROUP(43, rmii, wifi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
603 PINGROUP(44, rmii, blsp_spi1, smart0, led5, NA, NA, NA, NA, NA, NA, NA,
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul-kontron-sl-common.dtsi37 phy-mode = "rmii";
49 clock-names = "rmii-ref";
55 phy-mode = "rmii";
H A Dimx53-kp-hsc.dts18 fixed-link { /* RMII fixed link to LAN9303 */
35 port@0 { /* RMII fixed link to master */
H A Dimx6ull-seeed-npi-dev-board.dtsi119 phy-mode = "rmii";
127 phy-mode = "rmii";
140 clock-names = "rmii-ref";
148 clock-names = "rmii-ref";
/linux/Documentation/devicetree/bindings/clock/
H A Dstarfive,jh7110-aoncrg.yaml23 - description: GMAC0 RMII reference or GMAC0 RGMII RX
30 - description: GMAC0 RMII reference or GMAC0 RGMII RX
38 - description: GMAC0 RMII reference
/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9x25ek.dts22 phy-mode = "rmii";
27 phy-mode = "rmii";
/linux/Documentation/networking/dsa/
H A Dsja1105.rst329 RMII PHY role and out-of-band signaling
332 In the RMII spec, the 50 MHz clock signals are either driven by the MAC or by
337 On the other hand, the SJA1105 is only binary configurable - when in the RMII
339 happening it must be put in RMII PHY role.
341 In the RMII spec, the PHY can transmit extra out-of-band signals via RXD[1:0].
344 mechanism defined by the RMII spec.
346 clock signal, inevitably an RMII PHY-to-PHY connection is created. The SJA1105
355 The take-away is that in RMII mode, the SJA1105 must be let to drive the
/linux/Documentation/devicetree/bindings/phy/
H A Dti,phy-gmii-sel.yaml15 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
31 | | | RMII <------->
154 - RMII refclk mode
/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-icev2.dts204 /* Slave 1, RMII mode */
213 /* Slave 2, RMII mode */
471 /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */
479 phy-mode = "rmii";
485 phy-mode = "rmii";
/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf610-bk4.dts161 phy-mode = "rmii";
174 clock-names = "rmii-ref";
180 phy-mode = "rmii";
193 clock-names = "rmii-ref";
/linux/arch/arm/boot/dts/st/
H A Dstm32mp151a-prtt1c.dts282 phy-mode = "rmii";
289 phy-mode = "rmii";
296 phy-mode = "rmii";
311 phy-mode = "rmii";

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