Home
last modified time | relevance | path

Searched +full:rmii +full:- +full:clk +full:- +full:from +full:- +full:mac (Results 1 – 19 of 19) sorted by relevance

/linux/Documentation/devicetree/bindings/net/
H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
[all …]
H A Dmediatek,star-emac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek STAR Ethernet MAC Controller
10 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
13 This Ethernet MAC is used on the MT8* family of SoCs from MediaTek.
14 It's compliant with 802.3 standards and supports half- and full-duplex
15 modes with flow-control as well as CRC offloading and VLAN tags.
18 - $ref: ethernet-controller.yaml#
[all …]
H A Dnxp,dwmac-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clark Wang <xiaoning.wang@nxp.com>
11 - Shawn Guo <shawnguo@kernel.org>
12 - NXP Linux Team <linux-imx@nxp.com>
20 - nxp,imx8mp-dwmac-eqos
21 - nxp,imx8dxl-dwmac-eqos
22 - nxp,imx93-dwmac-eqos
[all …]
H A Dsti-dwmac.txt10 - compatible : "st,stih407-dwmac"
11 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
13 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
15 - pinctrl-0: pin-control for all the MII mode supported.
18 - resets : phandle pointing to the system reset controller with correct
20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
21 MAC can generate it.
22 - st,tx-retime-src: This specifies which clk is wired up to the mac for
24 possible values from "txclk", "clk_125" or "clkgen".
26 - sti-ethclk: this is the phy clock.
[all …]
/linux/drivers/clk/
H A Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
48 /* clk rst name parent flags */
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
[all …]
/linux/drivers/net/ethernet/faraday/
H A Dftgmac100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
11 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
54 /* For NC-SI to register a fixed-link phy device */
100 struct clk *clk; member
102 /* AST2500/AST2600 RMII ref clock gate */
103 struct clk *rclk;
126 struct net_device *netdev = priv->netdev; in ftgmac100_reset_mac()
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-sun8i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
8 #include <linux/clk.h>
11 #include <linux/mdio-mux.h>
28 /* General notes on dwmac-sun8i:
33 /* struct emac_variant - Describe dwmac-sun8i hardware variant
39 * @soc_has_internal_phy: Does the MAC embed an internal PHY
40 * @support_mii: Does the MAC handle MII
41 * @support_rmii: Does the MAC handle RMII
42 * @support_rgmii: Does the MAC handle RGMII
[all …]
/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc3250-phy3250.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PHYTEC phyCORE-LPC3250 board
5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
9 /dts-v1/;
13 model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
22 compatible = "gpio-leds";
26 default-state = "off";
31 linux,default-trigger = "heartbeat";
37 power-supply = <&reg_lcd>;
41 remote-endpoint = <&cldc_output>;
[all …]
H A Dlpc3250-ea3250.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
20 gpio-keys {
21 compatible = "gpio-keys";
86 compatible = "gpio-leds";
92 linux,default-trigger = "timer";
93 default-state = "off";
98 default-state = "off";
103 default-state = "off";
108 default-state = "off";
[all …]
/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
27 Currently, this network device driver is for all STi embedded MAC/GMAC
32 DesignWare(R) Cores Ethernet MAC 10/100/1000 Universal version 3.70a
[all …]
/linux/arch/sh/boards/mach-se/7724/
H A Dsetup.c1 // SPDX-License-Identifier: GPL-2.0
35 #include <linux/dma-map-ops.h>
37 #include <mach-se/mach/se7724.h>
38 #include <media/drv-intf/renesas-ceu.h>
51 * ------------------------------------
55 * SW41 : abxx xxxx -> a = 0 : Analog monitor
65 * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz,
73 * Please change J20, J21, J22 pin to 1-2 connection.
85 .id = -1,
123 .mask_flags = MTD_WRITEABLE, /* Read-only */
[all …]
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_clocking.c1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2016-2018 NXP
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
107 sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op); in sja1105_cgu_idiv_packing()
108 sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op); in sja1105_cgu_idiv_packing()
109 sja1105_packing(buf, &idiv->idiv, 5, 2, size, op); in sja1105_cgu_idiv_packing()
110 sja1105_packing(buf, &idiv->pd, 0, 0, size, op); in sja1105_cgu_idiv_packing()
116 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_idiv_config()
117 struct device *dev = priv->ds->dev; in sja1105_cgu_idiv_config()
121 if (regs->cgu_idiv[port] == SJA1105_RSV_ADDR) in sja1105_cgu_idiv_config()
[all …]
/linux/arch/sh/boards/mach-ecovec24/
H A Dsetup.c1 // SPDX-License-Identifier: GPL-2.0
39 #include <linux/dma-map-ops.h>
41 #include <media/drv-intf/renesas-ceu.h>
52 *-----------------------------------------
62 *------------------------------
65 * DS2[2] = RMII / TS, SCIF ON : RMII
71 * DS2[6-7] = MMC / SD ON-OFF : SD
72 * OFF-ON : MMC
76 * FSI - DA7210
99 .end = 0xA405012E - 1,
[all …]
/linux/drivers/net/ethernet/cadence/
H A Dmacb_main.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2006 Atmel Corporation
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
40 #include <linux/firmware/xlnx-zynqmp.h>
58 * (bp)->rx_ring_size)
64 * (bp)->tx_ring_size)
67 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
78 …MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN -…
[all …]
/linux/drivers/net/ethernet/freescale/
H A Dfec_main.c1 // SPDX-License-Identifier: GPL-2.0+
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
52 #include <linux/clk.h>
194 { .compatible = "fsl,imx25-fec", .data = &fec_imx25_info, },
195 { .compatible = "fsl,imx27-fec", .data = &fec_imx27_info, },
196 { .compatible = "fsl,imx28-fec", .data = &fec_imx28_info, },
197 { .compatible = "fsl,imx6q-fec", .data = &fec_imx6q_info, },
198 { .compatible = "fsl,mvf600-fec", .data = &fec_mvf600_info, },
[all …]
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_star_emac.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
67 /* MAC Configuration Register */
77 /* Flow-Control Configuration Register */
90 /* MAC High and Low Bytes Registers */
133 /* Delay-Macro Register */
154 /* MAC Clock Configuration Register */
200 /* Represents the actual structure of descriptors used by the MAC. We can
201 * reuse the same structure for both TX and RX - the layout is the same, only
[all …]
/linux/drivers/net/phy/
H A Dmicrel.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2010-2013 Micrel, Inc.
29 #include <linux/clk.h>
126 * The value is calculated as following: (1/1000000)/((2^-32)/4)
132 * The value is calculated as following: (1/1000000)/((2^-32)/8)
284 /* Write/read to/from extended registers */
360 /* Delay used to get the second part from the LTC */
435 struct clk *clk; member
527 const struct kszphy_type *type = phydev->drv->driver_data; in kszphy_config_intr()
531 if (type && type->interrupt_level_mask) in kszphy_config_intr()
[all …]
/linux/drivers/net/dsa/microchip/
H A Dksz8.c1 // SPDX-License-Identifier: GPL-2.0
6 * - KSZ8863, KSZ8873 aka KSZ88X3
7 * - KSZ8895, KSZ8864 aka KSZ8895 family
8 * - KSZ8794, KSZ8795, KSZ8765 aka KSZ87XX
10 * - KSZ8563, KSZ8567 - see KSZ9477 driver
23 #include <linux/platform_data/microchip-ksz.h>
49 * ksz8_ind_write8 - EEE/ACL/PME indirect register write
56 * PME switch functionalities. Both 8-bit registers 110 and 111 are
68 regs = dev->info->regs; in ksz8_ind_write8()
70 mutex_lock(&dev->alu_mutex); in ksz8_ind_write8()
[all …]
/linux/arch/powerpc/include/asm/
H A Dcpm2.h1 /* SPDX-License-Identifier: GPL-2.0 */
27 /* Device sub-block and page codes.
72 /* CPM2-specific opcodes (see cpm.h for common opcodes)
106 extern void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src);
124 /* Parameter RAM offsets from the base.
153 * get some microcode patches :-).
154 * The parameter ram space for the SMCs is fifty-some bytes, and
353 uint sen_tbuf0data0; /* Save area 0 - current frame */
354 uint sen_tbuf0data1; /* Save area 1 - current frame */
365 uint sen_tbuf1data0; /* Save area 0 - current frame */
[all …]