Home
last modified time | relevance | path

Searched +full:rk3588 +full:- +full:pcie +full:- +full:ep (Results 1 – 5 of 5) sorted by relevance

/linux/Documentation/devicetree/bindings/pci/
H A Drockchip-dw-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe Endpoint controller on Rockchip SoCs
10 - Niklas Cassel <cassel@kernel.org>
13 RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare
14 PCIe IP and thus inherits all the common properties defined in
15 snps,dw-pcie-ep.yaml.
18 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-extra.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk3588-base.dtsi"
7 #include "rk3588-extra-pinctrl.dtsi"
11 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
16 clock-names = "ref_clk", "suspend_clk", "bus_clk";
19 phy-names = "usb2-phy", "usb3-phy";
21 power-domains = <&power RK3588_PD_USB>;
24 snps,dis-u2-freeclk-exists-quirk;
25 snps,dis-del-phy-power-chg-quirk;
26 snps,dis-tx-ipgap-linecheck-quirk;
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
3 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb
4 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb
5 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb
6 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-firefly-jd4-core-mb.dtb
7 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou.dtb
8 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb
9 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb
10 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb
[all …]
H A Drk3588-rock-5b-pcie-ep.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode
7 * RC mode and the other board running in EP mode, see also the device
8 * tree overlay: rk3588-rock-5b-pcie-srns.dtso.
11 /dts-v1/;
15 rockchip,rx-common-refclk-mode = <0 0 0 0>;
23 vpcie3v3-supply = <&vcc3v3_pcie30>;
/linux/drivers/pci/controller/dwc/
H A Dpcie-dw-rockchip.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Rockchip SoCs.
6 * http://www.rock-chips.com
8 * Author: Simon Xue <xxm@rock-chips.com>
24 #include "pcie-designware.h"
34 #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
77 return readl_relaxed(rockchip->apb_base + reg); in rockchip_pcie_readl_apb()
83 writel_relaxed(val, rockchip->apb_base + reg); in rockchip_pcie_writel_apb()
97 generic_handle_domain_irq(rockchip->irq_domain, hwirq); in rockchip_pcie_intx_handler()
105 HIWORD_UPDATE_BIT(BIT(data->hwirq)), in rockchip_intx_mask()
[all …]