Searched +full:rk3399 +full:- +full:ddr (Results 1 – 7 of 7) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Rockchip rk3399 DMC (Dynamic Memory Controller) device10 - Brian Norris <briannorris@chromium.org>15 - rockchip,rk3399-dmc17 devfreq-events:20 Node to get DDR loading. Refer to26 clock-names:[all …]
1 // SPDX-License-Identifier: GPL-2.0-only4 * Author: Lin Huang <hl@rock-chips.com>7 #include <linux/arm-smccc.h>12 #include <linux/devfreq-event.h>75 unsigned long old_clk_rate = dmcfreq->rate; in rk3399_dmcfreq_target()93 if (dmcfreq->rate == target_rate) in rk3399_dmcfreq_target()96 mutex_lock(&dmcfreq->lock); in rk3399_dmcfreq_target()99 * Ensure power-domain transitions don't interfere with ARM Trusted in rk3399_dmcfreq_target()100 * Firmware power-domain idling. in rk3399_dmcfreq_target()109 * Some idle parameters may be based on the DDR controller clock, which in rk3399_dmcfreq_target()[all …]
1 # SPDX-License-Identifier: GPL-2.0-only20 to a device by 1-to-1. The device registering devfreq takes the39 Simple-Ondemand should be able to provide busy/total counter89 PPMU counters of memory controllers by using DEVFREQ-event device118 This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows144 tristate "ARM RK3399 DMC DEVFREQ Driver"151 This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
1 # SPDX-License-Identifier: GPL-2.06 obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o8 clk-rockchip-y += clk.o9 clk-rockchip-y += clk-pll.o10 clk-rockchip-y += clk-cpu.o11 clk-rockchip-y += clk-gate-grf.o12 clk-rockchip-y += clk-half-divider.o13 clk-rockchip-y += clk-inverter.o14 clk-rockchip-y += clk-mmc-phase.o15 clk-rockchip-y += clk-muxgrf.o[all …]
1 // SPDX-License-Identifier: GPL-2.0-only4 * Author: Lin Huang <hl@rock-chips.com>8 #include <linux/devfreq-event.h>67 * struct dmc_count_channel - structure to hold counter values from the DDR controller69 * @clock_cycles: DDR clock cycles85 * The dfi controller can monitor DDR load. It has an upper and lower threshold87 * generated to indicate the DDR frequency should be changed.118 bool lp5_ckr; /* true if in 4:1 command-to-data clock ratio mode */126 switch (dfi->ddr_type) { in rockchip_dfi_ddrtype_to_ctrl()140 ddrmon_ver = readl_relaxed(dfi->regs); in rockchip_dfi_ddrtype_to_ctrl()[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)7 #include <dt-bindings/clock/rk3308-cru.h>8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/interrupt-controller/irq.h>11 #include <dt-bindings/pinctrl/rockchip.h>12 #include <dt-bindings/soc/rockchip,boot-mode.h>13 #include <dt-bindings/thermal/thermal.h>18 interrupt-parent = <&gic>;19 #address-cells = <2>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)5 * Copyright 2016-2017 Google, Inc8 #include <dt-bindings/input/input.h>9 #include "rk3399-op1.dtsi"18 stdout-path = "serial2:115200n8";27 * - Rails that only connect to the EC (or devices that the EC talks to)29 * - Rails _are_ included if the rails go to the AP even if the AP38 * - The EC controls the enable and the EC always enables a rail as40 * - The rails are actually connected to each other by a jumper and45 ppvar_sys: regulator-ppvar-sys {[all …]