Searched +full:riscv +full:- +full:zicond (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)3 ---4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: RISC-V ISA extensions10 - Paul Walmsley <paul.walmsley@sifive.com>11 - Palmer Dabbelt <palmer@sifive.com>12 - Conor Dooley <conor@kernel.org>15 RISC-V has a large number of extensions, some of which are "standard"16 extensions, meaning they are ratified by RISC-V International, and others[all …]
1 //===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception7 //===----------------------------------------------------------------------===//9 // This file defines the interfaces that RISC-V uses to lower LLVM code into a12 //===----------------------------------------------------------------------===//17 #include "RISCV.h"30 // clang-format off37 /// Select with condition operator - This selects between a true value and57 // Selected as PseudoAddTPRel. Used to emit a TP-relative relocation.68 // RV64I shifts, directly matching the semantics of the named RISC-V[all …]
1 //===-- RISCVFeatures.td - RISC-V Features and Extensions --*- tablegen -*-===//5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception7 //===----------------------------------------------------------------------===//9 //===----------------------------------------------------------------------===//10 // RISC-V subtarget features and instruction predicates.11 //===----------------------------------------------------------------------===//13 // Subclass of SubtargetFeature to be used when the feature is also a RISC-V16 // name - Name of the extension in lower case.17 // major - Major version of extension.18 // minor - Minor version of extension.[all …]
1 //===-- RISCVISelLowering.cpp - RISC-V DAG Lowering Implementation ------[all...]