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/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
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/linux/arch/riscv/
H A DMakefile2 # architecture-specific flags and dependencies.
9 LDFLAGS_vmlinux := -z norelro
11 LDFLAGS_vmlinux += -shared -Bsymbolic -z notext
12 KBUILD_CFLAGS += -fPIE
15 LDFLAGS_vmlinux += --no-relax
16 KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY
18 CC_FLAGS_FTRACE := -fpatchable-function-entry=8,4
20 CC_FLAGS_FTRACE := -fpatchable-function-entry=4,2
25 KBUILD_CFLAGS_MODULE += -mcmodel=medany
33 KBUILD_CFLAGS += -mabi=lp64
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
13 config RISCV config
65 # clang >= 17: https://github.com/llvm/llvm-project/commit/62fa708ceb027713b386c7e0efda994f8bdc27e2
236 # -Zsanitizer=shadow-call-stack flag.
246 depends on $(cc-option,-fpatchable-function-entry=8)
250 def_bool $(cc-option,-fsanitize=shadow-call-stack)
251 …# https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/a484e843e6eeb51f0cb7b8819e50da6d2444…
252 depends on $(ld-option,--no-relax-gp)
254 # https://github.com/llvm/llvm-project/commit/bbc0f99f3bc96f1db16f649fc21dd18e5b0918f6
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/linux/Documentation/arch/riscv/
H A Dhwprobe.rst1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Hardware Probing Interface
4 ---------------------------------
6 The RISC-V hardware probing interface is based around a single syscall, which
18 The arguments are split into three groups: an array of key-value pairs, a CPU
19 set, and some flags. The key-value pairs are supplied with a count. Userspace
22 will be cleared to -1, and its value set to 0. The CPU set is defined by
23 CPU_SET(3) with size ``cpusetsize`` bytes. For value-like keys (eg. vendor,
25 have the same value. Otherwise -1 will be returned. For boolean-like keys, the
33 by sys_riscv_hwprobe() to only those which match each of the key-value pairs.
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H A Dvector.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Vector Extension Support for RISC-V Linux
8 order to support the use of the RISC-V Vector Extension.
11 ---------------------
15 these interfaces is to give init systems a way to modify the availability of V
19 are not portable to non-Linux, nor non-RISC-V environments, so it is discourage
20 to use in a portable code. To get the availability of V in an ELF program,
27 argument consists of two 2-bit enablement statuses and a bit for inheritance
30 Enablement status is a tri-state value each occupying 2-bit of space in
33 * :c:macro:`PR_RISCV_V_VSTATE_CTRL_DEFAULT`: Use the system-wide default
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21 Each interrupt can be enabled on per-context basis. Any context can claim
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/linux/arch/riscv/mm/
H A Dcacheflush.c1 // SPDX-License-Identifier: GPL-2.0-only
30 * the IPI. The RISC-V spec states that a hart must execute a data fence in flush_icache_all()
34 * IPIs on RISC-V are triggered by MMIO writes to either CLINT or in flush_icache_all()
35 * S-IMSIC, so the fence ensures previous data writes "happen before" in flush_icache_all()
48 * Performs an icache flush for the given MM context. RISC-V has no direct
52 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
65 mask = &mm->context.icache_stale_mask; in flush_icache_mm()
78 if (mm == current->active_mm && local) { in flush_icache_mm()
104 if (!test_bit(PG_dcache_clean, &folio->flags.f)) { in flush_icache_pte()
106 set_bit(PG_dcache_clean, &folio->flags.f); in flush_icache_pte()
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/linux/arch/riscv/kernel/
H A Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <asm/text-patching.h>
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
43 /* Per-cpu ISA extensions. */
49 * riscv_isa_extension_base() - Get base extension word
63 * __riscv_isa_extension_available() - Check whether given extension
89 return -EPROBE_DEFER; in riscv_ext_f_depends()
96 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_ext_zicbom_validate()
97 return -EINVAL; in riscv_ext_zicbom_validate()
100 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); in riscv_ext_zicbom_validate()
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H A Dacpi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V Specific Low-Level ACPI Boot Support
5 * Copyright (C) 2013-2014, Linaro Ltd.
12 * Copyright (C) 2021-2023, Ventana Micro Systems Inc.
13 * Author: Sunil V L <sunilvl@ventanamicro.com>
17 #include <linux/efi-bgrt.h>
41 return -EINVAL; in parse_acpi()
51 return -EINVAL; /* Core will print when we return error */ in parse_acpi()
58 * acpi_fadt_sanity_check() - Check FADT presence and carry out sanity
71 * FADT is required on riscv; retrieve it to check its presence in acpi_fadt_sanity_check()
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/linux/drivers/irqchip/
H A Dirq-sifive-plic.c1 // SPDX-License-Identifier: GPL-2.0
6 #define pr_fmt(fmt) "riscv-plic: " fmt
25 * This driver implements a version of the RISC-V PLIC with the actual layout
28 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
30 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
31 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
32 * Spec.
102 u32 __iomem *base = handler->enable_base; in __plic_toggle()
114 handler->enable_save[group] = value; in __plic_toggle()
122 raw_spin_lock_irqsave(&handler->enable_lock, flags); in plic_toggle()
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/linux/drivers/iommu/riscv/
H A Diommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for RISC-V IOMMU implementations.
5 * Copyright © 2022-2024 Rivos Inc.
6 * Copyright © 2023 FORTH-ICS/CARV
13 #define pr_fmt(fmt) "riscv-iommu: " fmt
25 #include "../iommu-pages.h"
26 #include "iommu-bits.h"
39 /* RISC-V IOMMU PPN <> PHYS address conversions, PHYS <=> PPN[53:10] */
40 #define phys_to_ppn(pa) (((pa) >> 2) & (((1ULL << 44) - 1) << 10))
41 #define ppn_to_phys(pn) (((pn) << 2) & (((1ULL << 44) - 1) << 12))
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/linux/Documentation/virt/kvm/
H A Dapi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
24 - System ioctls: These query and set global attributes which affect the
28 - VM ioctls: These query and set attributes that affect an entire virtual
35 - vcpu ioctls: These query and set attributes that control the operation
43 - device ioctls: These query and set attributes that control the operation
92 facility that allows backward-compatible extensions to the API to be
133 -----------------------
150 -----------------
189 address used by the VM. The IPA_Bits is encoded in bits[7-0] of the
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/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt39 Documentation/arch/m68k/kernel-options.rst.
49 PARISC The PA-RISC architecture is enabled.
60 RISCV RISCV architecture is enabled.
64 the Documentation/scsi/ sub-directory.
83 X86-32 X86-32, aka i386 architecture is enabled.
84 X86-64 X86-64 architecture is enabled.
85 X86 Either 32-bit or 64-bit x86 (same as X86-32+X86-64)
94 KNL Is a kernel start-up parameter.
114 force -- enable ACPI if default was off
115 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
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