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/freebsd/sys/contrib/device-tree/Bindings/perf/
H A Driscv,pmu.yaml1 # SPDX-License-Identifier: BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-
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/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Driscv,cpu-intc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
20 time timer that is controlled via Supervisor Binary Interface (SBI) calls
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H A Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
14 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
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/freebsd/sys/riscv/include/
H A Dsbi.h1 /*-
2 * Copyright (c) 2016-2017 Ruslan Bukin <br@bsdpad.com>
8 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
39 /* SBI Specification Version */
45 /* SBI Implementation IDs */
59 /* SBI Error Codes */
61 #define SBI_ERR_FAILURE -1
62 #define SBI_ERR_NOT_SUPPORTED -2
63 #define SBI_ERR_INVALID_PARAM -3
64 #define SBI_ERR_DENIED -4
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/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Driscv,timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
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/freebsd/sys/riscv/conf/
H A DNOTES2 # NOTES -- Lines that can be cut/pasted into kernel and hints configs.
9 cpu RISCV
11 makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
23 # RISC-V SBI console
41 # NOTE: dtrace introduces CDDL-licensed components into the kernel
47 device uart_ns8250 # ns8250-type UART driver
62 device xilinx_spi # Xilinx AXI Quad-SPI Controller
78 # FreeBSD/riscv did
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H A DGENERIC2 # GENERIC -- Generic kernel configuration file for FreeBSD/RISC-V
7 # https://docs.freebsd.org/en/books/handbook/kernelconfig/#kernelconfig-config
20 cpu RISCV
23 makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
42 options UFS_GJOURNAL # Enable gjournal-based UFS journaling
51 options PSEUDOFS # Pseudo-filesystem framework
61 options SYSVSHM # SYSV-style shared memory
62 options SYSVMSG # SYSV-style message queues
63 options SYSVSEM # SYSV-style semaphores
64 options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions
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/freebsd/sys/conf/
H A Dfiles.riscv1 cddl/dev/dtrace/riscv/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}"
2 cddl/dev/dtrace/riscv/dtrace_isa.c optional dtrace compile-with "${DTRACE_C}"
3 cddl/dev/dtrace/riscv/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}"
4 cddl/dev/dtrace/riscv/instr_size.c optional dtrace compile-with "${DTRACE_C}"
5 cddl/dev/fbt/riscv/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}"
40 riscv/riscv/aplic.c standard
41 riscv/riscv/autoconf.c standard
42 riscv/riscv/bus_machdep.c standard
43 riscv/riscv/bus_space_asm.S standard
44 riscv/riscv/busdma_bounce.c standard
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/freebsd/sys/riscv/riscv/
H A Driscv_console.c1 /*-
2 * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com>
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
66 #include <machine/sbi.h>
102 CONSOLE_DRIVER(riscv);
113 #if CHECK_EARLY_PRINTF(sbi)
161 while ((c = riscv_cngetc(NULL)) != -1) in riscv_timeout()
173 cp->cn_pri = CN_NORMAL; in riscv_cnprobe()
180 strcpy(cp->cn_name, "rcons"); in riscv_cninit()
214 return (-1); in riscv_cngetc()
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H A Dmp_machdep.c1 /*-
11 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
64 #include <machine/sbi.h>
111 void *dpcpu[MAXCPU - 1];
160 cpuid -= boot_hart; in init_secondary()
177 pcpup->pc_curthread = pcpup->pc_idlethread; in init_secondary()
184 /* Start per-CPU event timers. */ in init_secondary()
189 CPU_SET_ATOMIC(hart, &kernel_pmap->pm_active); in init_secondary()
319 if (OF_getprop(node, "mmu-type", (void *)type, sizeof(type)) == -1 || in cpu_check_mmu()
320 strncmp(type, "riscv,none", 10) == 0) in cpu_check_mmu()
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H A Dpmap.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
18 * Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com>
30 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
64 /*-
71 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
101 * this module may throw away valid virtual-to-physical
103 * of virtual-to-physical mappings must be done as
107 * make virtual-to-physical map invalidates expensive,
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/freebsd/usr.sbin/bhyve/riscv/
H A Dvmexit.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
40 #include <machine/sbi.h>
58 #include "riscv.h"
81 vme = vmrun->vm_exit; in vmexit_inst_emul()
82 vie = &vme->u.inst_emul.vie; in vmexit_inst_emul()
84 err = emulate_mem(vcpu, vme->u.inst_emul.gpa, vie, in vmexit_inst_emul()
85 &vme->u.inst_emul.paging); in vmexit_inst_emul()
89 vme->u.inst_emul.gpa); in vmexit_inst_emul()
98 FPRINTLN(stderr, "at 0x%lx", vme->pc); in vmexit_inst_emul()
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/freebsd/sys/riscv/vmm/
H A Dvmm_sbi.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
58 #include <machine/sbi.h>
60 #include "riscv.h"
76 func_id = hypctx->guest_regs.hyp_a[6]; in vmm_sbi_handle_rfnc()
77 hart_mask = hypctx->guest_regs.hyp_a[0]; in vmm_sbi_handle_rfnc()
78 hart_mask_base = hypctx->guest_regs.hyp_a[1]; in vmm_sbi_handle_rfnc()
82 fence.start = hypctx->guest_regs.hyp_a[2]; in vmm_sbi_handle_rfnc()
83 fence.size = hypctx->guest_regs.hyp_a[3]; in vmm_sbi_handle_rfnc()
84 fence.asid = hypctx->guest_regs.hyp_a[4]; in vmm_sbi_handle_rfnc()
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