Home
last modified time | relevance | path

Searched +full:riscv +full:- +full:code +full:- +full:size +full:- +full:reduction (Results 1 – 15 of 15) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMakeCompressible.cpp1 //===-- RISCVMakeCompressible.cpp - Make more instructions compressible ---===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
27 // to the following to improve code size:
43 // sw a1, -236(a2)
44 // sw a1, -240(a2)
45 // sw a1, -244(a2)
46 // sw a1, -248(a2)
47 // sw a1, -252(a2)
48 // sw a0, -256(a2)
[all …]
H A DRISCVTargetTransformInfo.cpp1 //===-- RISCVTargetTransformInfo.cpp - RISC-V specific TTI ----------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
26 "riscv-v-register-bit-width-lmul",
29 "by autovectorized code. Fractional LMULs are not supported."),
33 "riscv-v-slp-max-vf",
45 size_t NumInstr = OpCodes.size(); in getRISCVInstructionCost()
48 InstructionCost LMULCost = TLI->getLMULCost(VT); in getRISCVInstructionCost()
54 case RISCV::VRGATHER_VI: in getRISCVInstructionCost()
55 Cost += TLI->getVRGatherVICost(VT); in getRISCVInstructionCost()
[all …]
H A DRISCVInstrInfo.cpp1 //===-- RISCVInstrInfo.cpp - RISC-V Instruction Information -----*-
70 namespace llvm::RISCV { global() namespace
1514 unsigned Size = 0; getInstBundleLength() local
[all...]
H A DRISCVISelLowering.h1 //===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that RISC-V uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
17 #include "RISCV.h"
30 // clang-format off
37 /// Select with condition operator - This selects between a true value and
40 /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
57 // Selected as PseudoAddTPRel. Used to emit a TP-relative relocation.
[all …]
H A DRISCVISelLowering.cpp1 //===-- RISCVISelLowering.cpp - RISC-V DAG Lowering Implementation ------
172 unsigned Size = VT.getSizeInBits().getKnownMinValue(); RISCVTargetLowering() local
4454 int Size = Mask.size(); isInterleaveShuffle() local
4493 int Size = Mask.size(); isElementRotate() local
5266 int Size = Mask.size(); lowerVECTOR_SHUFFLE() local
9825 SDValue Reduction = DAG.getNode(RVVOpcode, DL, M1VT, Ops); lowerReductionSeq() local
12335 unsigned Size = N->getSimpleValueType(0).getSizeInBits(); ReplaceNodeResults() local
19941 unsigned Size = Flags.getByValSize(); LowerCall() local
20967 unsigned Size = AI->getType()->getPrimitiveSizeInBits(); shouldExpandAtomicRMWInIR() local
21099 unsigned Size = CI->getCompareOperand()->getType()->getPrimitiveSizeInBits(); shouldExpandAtomicCmpXchgInIR() local
[all...]
H A DRISCVFeatures.td1 //===-- RISCVFeatures.td - RISC-V Features and Extensions --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
10 // RISC-V subtarget features and instruction predicates.
11 //===----------------------------------------------------------------------===//
13 // Subclass of SubtargetFeature to be used when the feature is also a RISC-V
16 // name - Name of the extension in lower case.
17 // major - Major version of extension.
18 // minor - Minor version of extension.
[all …]
H A DRISCVInstrInfoVPseudos.td1 //===-- RISCVInstrInfoVPseudos.td - RISC-V 'V' Pseudos -----*- tablege
[all...]
/freebsd/share/man/man5/
H A Dsrc.conf.51 .\" DO NOT EDIT-- this file is @generated by tools/build/options/makeman.
40 may be necessary if the system-wide settings are not suitable
52 source code, which is usually located in
72 .Pa /etc/src-env.conf .
79 as they are environment-only variables.
96 .Bl -tag -width indent
114 memory corruption bugs such as buffer overflows or use-after-free.
119 .Bl -item -compact
147 .Pa /etc/src-env.conf ,
162 Due to size constraints in the BIOS environment on x86, one may need to set
[all …]
/freebsd/contrib/llvm-project/clang/include/clang/Support/
H A DRISCVVIntrinsicUtils.h1 //===--- RISCVVIntrinsicUtils.h - RISC-V Vector Intrinsic Utils -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
28 namespace RISCV {
102 // Widening2XVector for widening reduction.
104 // simple enum, so we decide keek LMUL1 in TypeModifier for code size
105 // optimization of clang binary size.
120 // policy generally will affect the performance of an out-of-order core.
354 // class, also provided thread-safe cache capability.
399 // InputTypes. -1 means the return type.
[all …]
/freebsd/contrib/llvm-project/clang/utils/TableGen/
H A DRISCVVEmitter.cpp1 //===- RISCVVEmitter.cpp - Generate riscv_vector.h for use with clang -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 // in https://github.com/riscv/rvv-intrinsic-doc.
15 //===----------------------------------------------------------------------===//
31 using namespace clang::RISCV;
107 /// Emit all the __builtin prototypes and code needed by Sema.
110 /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
167 static_cast<uint8_t>(VectorTypeModifier::Tuple2) + (NF - 2)); in getTupleVTM()
171 if (!RVVI->getIRName().empty()) in emitCodeGenSwitchBody()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp1 //===- SelectionDAG.cpp - Implement the SelectionDAG data structures ------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
87 /// makeVTList - Return an instance of the SDVTList struct initialized with the
104 static cl::opt<bool> EnableMemCpyDAGOpt("enable-memcpy-dag-opt",
108 static cl::opt<int> MaxLdStGlue("ldstmemcpy-glue-max",
113 LLVM_DEBUG(dbgs() << Msg; V.getNode()->dump(G);); in NewSDValueDbgMsg()
116 //===----------------------------------------------------------------------===//
118 //===----------------------------------------------------------------------===//
[all …]
H A DDAGCombiner.cpp1 //===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
88 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
89 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
99 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
103 UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
108 CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
109 cl::desc("Only use DAG-combiner alias analysis in this"
[all …]
/freebsd/contrib/llvm-project/clang/include/clang/Driver/
H A DOptions.td1 //===--- Options.td - Options for clang -----------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
38 // The option is a "driver"-only option, and should not be forwarded to other
39 // tools via `-Xarch` options.
42 // LinkerInput - The option is a linker input.
45 // NoArgumentUnused - Don't report argument unused warnings for this option; this
46 // is useful for options like -static or -dynamic which a user may always end up
50 // Unsupported - The option is unsupported, and the driver will reject command
[all …]
/freebsd/contrib/llvm-project/clang/include/clang/Sema/
H A DSema.h1 //===--- Sema.h - Semantic Analysis & AST Building --------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
268 /// placing fix-its.
284 /// A single-element cache based on the file ID.
292 // Check the single-element cache.
296 // It's not in the single-element cache; flush the cache if we have one.
308 /// Tracks expected type during expression parsing, for use in code completion.
329 /// The callback should also emit signature help as a side-effect, but only
[all …]