Searched +full:riscv +full:- +full:bitmanip (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)3 ---4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: RISC-V ISA extensions10 - Paul Walmsley <paul.walmsley@sifive.com>11 - Palmer Dabbelt <palmer@sifive.com>12 - Conor Dooley <conor@kernel.org>15 RISC-V has a large number of extensions, some of which are "standard"16 extensions, meaning they are ratified by RISC-V International, and others[all …]
1 //===-- RISCVFeatures.td - RISC-V Features and Extensions --*- tablegen -*-===//5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception7 //===----------------------------------------------------------------------===//9 //===----------------------------------------------------------------------===//10 // RISC-V subtarget features and instruction predicates.11 //===----------------------------------------------------------------------===//13 // Subclass of SubtargetFeature to be used when the feature is also a RISC-V16 // name - Name of the extension in lower case.17 // major - Major version of extension.18 // minor - Minor version of extension.[all …]
1 //===-- RISCVInstrInfo.td - Target Description for RISC-V --*- tablegen -*-===//5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception7 //===----------------------------------------------------------------------===//9 // This file describes the RISC-V instructions in TableGen format.11 //===----------------------------------------------------------------------===//13 //===----------------------------------------------------------------------===//14 // RISC-V specific DAG Nodes.15 //===----------------------------------------------------------------------===//17 // Target-independent type requirements, but with target-specific formats.23 // Target-dependent type requirements.[all …]
1 //===- IntrinsicsRISCV.td - Defines RISCV intrinsics -------*- tablegen -*-===//5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception7 //===----------------------------------------------------------------------===//9 // This file defines all of the RISCV-specific intrinsics.11 //===----------------------------------------------------------------------===//13 //===----------------------------------------------------------------------===//26 let TargetPrefix = "riscv" in {37 // We define 32-bit and 64-bit variants of the above, where T stands for i3257 // @llvm.riscv.masked.atomicrmw.*.{i32,i64}.<p>(66 // @llvm.riscv.masked.atomicrmw.{max,min}.{i32,i64}.<p>([all …]