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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id
[all...]
H A Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/net/adi,adin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
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H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
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H A Dxlnx,gmii-to-rgmii.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,gmii-to-rgmii.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx GMII to RGMII Converter
10 - Harini Katakam <harini.katakam@amd.com>
14 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
24 const: xlnx,gmii-to-rgmii-1.0
29 description: The ID number for the phy.
31 phy-handle:
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H A Damlogic,meson-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
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H A Dapm-xgene-enet.txt1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
[all …]
H A Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/net/qca,ar803x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Floria
[all...]
H A Dxilinx_gmii2rgmii.txt2 --------------------------------------------------------
5 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
18 - compatible : Should be "xlnx,gmii-to-rgmii-1.0"
19 - reg : The ID number for the phy, usually a small integer
20 - phy-handle : Should point to the external phy device.
25 #address-cells = <1>;
26 #size-cells = <0>;
27 phy: ethernet-phy@0 {
31 compatible = "xlnx,gmii-to-rgmii-1.0";
33 phy-handle = <&phy>;
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/ti,dp83867.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
25 Media Independent Interface (GMII) or Reduced GMII (RGMII).
34 nvmem-cells:
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H A Dti,icssg-prueth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,icssg-prueth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Md Danish Anwar <danishanwar@ti.com>
13 Ethernet based on the Programmable Real-Time Unit and Industrial
19 - ti,am642-icssg-prueth # for AM64x SoC family
20 - ti,am654-icssg-prueth # for AM65x SoC family
21 - ti,am654-sr1-icssg-prueth # for AM65x SoC family, SR1.0
32 dma-names:
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H A Dengleder,tsnep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id
[all...]
H A Dqcom,ethqos.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,ethqos.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
17 - $ref: snps,dwmac.yaml#
22 - qcom,qcs404-ethqos
23 - qcom,sa8775p-ethqos
24 - qcom,sc8280xp-ethqos
25 - qcom,sm8150-ethqos
[all …]
H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id
[all...]
/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dsja1105.txt6 - compatible:
8 - "nxp,sja1105e"
9 - "nxp,sja1105t"
10 - "nxp,sja1105p"
11 - "nxp,sja1105q"
12 - "nxp,sja1105r"
13 - "nxp,sja1105s"
15 Although the device ID could be detected at runtime, explicit bindings
18 and the non-SGMII devices, while pin-compatible, are not equal in terms
19 of support for RGMII internal delays (supported on P/Q/R/S, but not on
[all …]
H A Dnxp,sja1105.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id
[all...]
H A Darrow,xrs700x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/arrow,xrs700x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: dsa.yaml#/$defs/ethernet-ports
13 - George McCollister <george.mccollister@gmail.com>
18 RGMII ports and one RMII port and are managed via i2c or mdio.
23 - enum:
24 - arrow,xrs7003e
25 - arrow,xrs7003f
[all …]
H A Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id
[all...]
/freebsd/sys/contrib/device-tree/src/arm/nxp/ls/
H A Dls1021a-tsn.dts1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2018 NXP Semiconductors
6 /dts-v1/;
10 model = "NXP LS1021A-TSN Board";
11 compatible = "fsl,ls1021a-tsn", "fsl,ls1021a";
13 sys_mclk: clock-mclk {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <24576000>;
19 reg_vdda_codec: regulator-3V3 {
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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmvme7100.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
10 /include/ "mpc8641si-pre.dtsi"
37 phy-handle = <&phy0>;
38 phy-connection-type = "rgmii-id";
42 phy0: ethernet-phy@1 {
45 phy1: ethernet-phy@2 {
48 phy2: ethernet-phy@3 {
51 phy3: ethernet-phy@4 {
57 phy-handle = <&phy1>;
[all …]
H A Dsbc8641d.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
12 /include/ "mpc8641si-pre.dtsi"
35 compatible = "cfi-flash";
37 bank-width = <2>;
38 device-width = <2>;
39 #address-cells = <1>;
40 #size-cells = <1>;
44 read-only;
49 read-only;
58 read-only;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-zc1751-xm018-dc4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm01
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/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am654-idk.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include "k3-pinctrl.h"
17 ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
18 ethernet4 = "/icssg0-eth/ethernet-ports/port@1";
19 ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
20 ethernet6 = "/icssg1-eth/ethernet-ports/port@1";
[all …]
H A Dk3-am654-icssg2.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include "k3-pinctrl.h"
16 ethernet1 = "/icssg2-eth/ethernet-ports/port@0";
17 ethernet2 = "/icssg2-eth/ethernet-ports/port@1";
20 /* Ethernet node on PRU-ICSSG2 */
21 icssg2_eth: icssg2-eth {
22 compatible = "ti,am654-icssg-prueth";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp151c-mect1s.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
10 #include "stm32mp15-pinctrl.dtsi"
11 #include "stm32mp15xxaa-pinctrl.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/leds/common.h>
21 stdout-path = "serial0:1500000n8";
33 v3v3: regulator-v3v3 {
34 compatible = "regulator-fixed";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dstarfive,jh7110-aoncrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Always-On Clock and Reset Generator
10 - Emil Renner Berthing <kernel@esmil.dk>
14 const: starfive,jh7110-aoncrg
21 - items:
22 - description: Main Oscillator (24 MHz)
23 - description: GMAC0 RMII reference or GMAC0 RGMII RX
[all …]

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