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/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dzynq-reset.txt1 Xilinx Zynq Reset Manager
8 - compatible: "xlnx,zynq-reset"
12 - #reset-cells: Must be 1
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
20 #reset-cells = <1>;
24 Reset outputs:
25 0 : soft reset
26 32 : ddr reset
27 64 : topsw reset
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H A Dsocionext,uniphier-reset.yaml4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-reset.yaml#
7 title: UniPhier reset controller
15 - description: System reset
17 - socionext,uniphier-ld4-reset
18 - socionext,uniphier-pro4-reset
19 - socionext,uniphier-sld8-reset
20 - socionext,uniphier-pro5-reset
21 - socionext,uniphier-pxs2-reset
22 - socionext,uniphier-ld6b-reset
23 - socionext,uniphier-ld11-reset
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H A Dreset.txt1 = Reset Signal Device Tree Bindings =
3 This binding is intended to represent the hardware reset signals present
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
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H A Dti-syscon-reset.txt1 TI SysCon Reset Controller
4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
12 A SysCon Reset Controller node defines a device that uses a syscon node
13 and provides reset management functionality for various hardware modules
16 SysCon Reset Controller Node
18 Each of the reset provider/controller nodes should be a child of a syscon
27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consume
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H A Damlogic,meson-reset.yaml5 $id: http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml#
8 title: Amlogic Meson SoC Reset Controller
17 - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
18 - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
19 - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
20 - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
21 - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs
22 - amlogic,c3-reset # Reset Controller on C3 and compatible SoCs
23 - amlogic,t7-reset
26 - amlogic,a4-reset
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H A Dsocionext,uniphier-glue-reset.yaml4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
7 title: Socionext UniPhier peripheral core reset in glue layer
10 Some peripheral core reset belongs to its own glue layer. Before using
11 this core reset, it is necessary to control the clocks and resets to
21 - socionext,uniphier-pro4-usb3-reset
22 - socionext,uniphier-pro5-usb3-reset
23 - socionext,uniphier-pxs2-usb3-reset
24 - socionext,uniphier-ld20-usb3-reset
25 - socionext,uniphier-pxs3-usb3-reset
26 - socionext,uniphier-nx1-usb3-reset
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H A Dxlnx,zynqmp-reset.yaml4 $id: http://devicetree.org/schemas/reset/xlnx,zynqmp-reset.yaml#
7 title: Zynq UltraScale+ MPSoC and Versal reset
15 The PS reset subsystem is responsible for handling the external reset
16 input to the device and that all internal reset requirements are met
19 Please also refer to reset.txt in this directory for common reset
20 controller binding usage. Device nodes that need access to reset
21 lines should specify them as a reset phandle in their corresponding
22 node as specified in reset.txt.
24 For list of all valid reset indices for Zynq UltraScale+ MPSoC
25 <dt-bindings/reset/xlnx-zynqmp-resets.h>
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H A Dfsl,imx7-src.txt1 Freescale i.MX7 System Reset Controller
4 Please also refer to reset.txt in this directory for common reset
17 - #reset-cells: 1, see below
21 src: reset-controller@30390000 {
25 #reset-cells = <1>;
29 Specifying reset lines connected to IP modules
32 The system reset controller can be used to reset various set of
33 peripherals. Device nodes that need access to reset lines should
34 specify them as a reset phandle in their corresponding node as
35 specified in reset.txt.
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H A Dsnps,hsdk-reset.txt1 Binding for the Synopsys HSDK reset controller
3 This binding uses the common reset binding[1].
5 [1] Documentation/devicetree/bindings/reset/reset.txt
8 - compatible: should be "snps,hsdk-reset".
9 - reg: should always contain 2 pairs address - length: first for reset
10 configuration register and second for corresponding SW reset and status bits
12 - #reset-cells: from common reset binding; Should always be set to 1.
15 reset: reset@880 {
16 compatible = "snps,hsdk-reset";
17 #reset-cells = <1>;
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H A Dimg,pistachio-reset.txt1 Pistachio Reset Controller
4 This binding describes a reset controller device that is used to enable and
5 disable individual IP blocks within the Pistachio SoC using "soft reset"
8 The actual action taken when soft reset is asserted is hardware dependent.
13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
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H A Duniphier-reset.txt1 UniPhier glue reset controller
4 Peripheral core reset in glue layer
7 Some peripheral core reset belongs to its own glue layer. Before using
8 this core reset, it is necessary to control the clocks and resets to enable
13 "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
14 "socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3
15 "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
16 "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
17 "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
18 "socionext,uniphier-pro4-ahci-reset" - for Pro4 SoC AHCI
[all …]
/freebsd/sys/dev/ice/
H A Dice_hw_autogen.h43 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE(_i) (0x000FD000 + ((_i) * 64)) /* _i=0...7 */ /* Reset Source: CORER */
67 #define GL_RDPU_CNTRL 0x00052054 /* Reset Source: CORER */
90 #define MSIX_PBA(_i) (0x00008000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: FLR */
94 #define MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
100 #define MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
104 #define MSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
108 #define PF0_FW_HLP_ARQBAH_PAGE 0x02D00180 /* Reset Source: EMPR */
111 #define PF0_FW_HLP_ARQBAL_PAGE 0x02D00080 /* Reset Source: EMPR */
116 #define PF0_FW_HLP_ARQH_PAGE 0x02D00380 /* Reset Source: EMPR */
119 #define PF0_FW_HLP_ARQLEN_PAGE 0x02D00280 /* Reset Sourc
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/freebsd/sys/dev/ixl/
H A Di40e_register.h38 #define I40E_GL_ARQBAH 0x000801C0 /* Reset: EMPR */
41 #define I40E_GL_ARQBAL 0x000800C0 /* Reset: EMPR */
44 #define I40E_GL_ARQH 0x000803C0 /* Reset: EMPR */
47 #define I40E_GL_ARQT 0x000804C0 /* Reset: EMPR */
50 #define I40E_GL_ATQBAH 0x00080140 /* Reset: EMPR */
53 #define I40E_GL_ATQBAL 0x00080040 /* Reset: EMPR */
56 #define I40E_GL_ATQH 0x00080340 /* Reset: EMPR */
59 #define I40E_GL_ATQLEN 0x00080240 /* Reset: EMPR */
70 #define I40E_GL_ATQT 0x00080440 /* Reset: EMPR */
73 #define I40E_PF_ARQBAH 0x00080180 /* Reset: EMPR */
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/freebsd/sys/contrib/device-tree/Bindings/power/reset/
H A Dkeystone-reset.txt1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
18 reset control registers.
26 - ti,soft-reset: Boolean option indicating soft reset.
27 By default hard reset is used.
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dqcom,pcie.yaml64 # Common definitions for clocks, clock-names and reset.
88 reset-names:
258 reset-names:
261 - const: axi # AXI reset
262 - const: ahb # AHB reset
263 - const: por # POR reset
264 - const: pci # PCI reset
265 - const: phy # PHY reset
266 - const: ext # EXT reset, not on apq8064
291 reset-names:
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H A Dqcom,pcie.txt195 Definition: List of phandle and reset specifier pairs as listed
196 in reset-names property
198 - reset-names:
202 - "axi" AXI reset
203 - "ahb" AHB reset
204 - "por" POR reset
205 - "pci" PCI reset
206 - "phy" PHY reset
208 - reset-names:
212 - "core" Core reset
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/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Ds8001-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
48 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
83 #reset-cells = <0>;
91 #reset-cells = <0>;
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H A Dt8103-pmgr.dtsi14 #reset-cells = <0>;
23 #reset-cells = <0>;
32 #reset-cells = <0>;
41 #reset-cells = <0>;
49 #reset-cells = <0>;
57 #reset-cells = <0>;
65 #reset-cells = <0>;
73 #reset-cells = <0>;
82 #reset-cells = <0>;
91 #reset-cells = <0>;
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H A Dt8112-pmgr.dtsi14 #reset-cells = <0>;
23 #reset-cells = <0>;
32 #reset-cells = <0>;
41 #reset-cells = <0>;
49 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
84 #reset-cells = <0>;
93 #reset-cells = <0>;
[all …]
H A Dt8015-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
49 #reset-cells = <0>;
58 #reset-cells = <0>;
67 #reset-cells = <0>;
76 #reset-cells = <0>;
84 #reset-cells = <0>;
93 #reset-cells = <0>;
[all …]
H A Dt8011-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
49 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
84 #reset-cells = <0>;
92 #reset-cells = <0>;
[all …]
H A Ds5l8960x-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
49 #reset-cells = <0>;
58 #reset-cells = <0>;
67 #reset-cells = <0>;
76 #reset-cells = <0>;
85 #reset-cells = <0>;
93 #reset-cells = <0>;
[all …]
H A Dt8012-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
48 #reset-cells = <0>;
57 #reset-cells = <0>;
65 #reset-cells = <0>;
74 #reset-cells = <0>;
83 #reset-cells = <0>;
91 #reset-cells = <0>;
[all …]
H A Dt8010-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
48 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
83 #reset-cells = <0>;
91 #reset-cells = <0>;
[all …]
H A Dt7001-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
49 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
84 #reset-cells = <0>;
92 #reset-cells = <0>;
[all …]

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