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/linux/Documentation/watchdog/
H A Dmlx-wdt.rst17 e.g. timeout 20 sec will be rounded up to 32768 msec.
18 The maximum timeout period is 32 sec (32768 msec.),
19 Get time-left isn't supported
22 Actual HW timeout is defined in sec. and it's the same as
23 a user-defined timeout.
24 Maximum timeout is 255 sec.
25 Get time-left is supported.
29 Maximum timeout is 65535 sec.
44 system reset, start fans on full speed and increase register counter.
45 The last 2 actions are performed without a system reset.
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/linux/arch/mips/dec/
H A Dtime.c1 // SPDX-License-Identifier: GPL-2.0
6 * This file contains the time handling details for PC-style clocks as
15 #include <asm/cpu-features.h>
17 #include <asm/time.h>
24 unsigned int year, mon, day, hour, min, sec, real_year; in read_persistent_clock64() local
30 sec = CMOS_READ(RTC_SECONDS); in read_persistent_clock64()
37 * The PROM will reset the year to either '72 or '73. in read_persistent_clock64()
42 } while (sec != CMOS_READ(RTC_SECONDS)); in read_persistent_clock64()
47 sec = bcd2bin(sec); in read_persistent_clock64()
55 year += real_year - 72 + 2000; in read_persistent_clock64()
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/linux/arch/mips/include/asm/
H A Dmc146818-time.h13 #include <linux/time.h>
42 save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */ in mc146818_set_rtc_mmss()
52 * messing with unknown time zones but requires your in mc146818_set_rtc_mmss()
57 if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) in mc146818_set_rtc_mmss()
58 real_minutes += 30; /* correct for half hour time zone */ in mc146818_set_rtc_mmss()
61 if (abs(real_minutes - cmos_minutes) < 30) { in mc146818_set_rtc_mmss()
72 retval = -1; in mc146818_set_rtc_mmss()
77 * battery and quartz) will not reset the oscillator and will not in mc146818_set_rtc_mmss()
80 * sheets anyway ... -- Markus Kuhn in mc146818_set_rtc_mmss()
91 unsigned int year, mon, day, hour, min, sec; in mc146818_get_cmos_time() local
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/linux/Documentation/devicetree/bindings/watchdog/
H A Datmel,at91sam9-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/watchdog/atmel,at91sam9-wdt.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Eugen Hristev <eugen.hristev@microchip.com>
15 const: atmel,at91sam9260-wdt
26 atmel,max-heartbeat-sec:
32 atmel,min-heartbeat-sec:
35 must be smaller than the max-heartbeat-sec value. It is used to
39 atmel,watchdog-type:
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H A Dst_lpc_wdt.txt1 STMicroelectronics Low Power Controller (LPC) - Watchdog
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
7 [See: ../rtc/rtc-st-lpc.txt for RTC options]
8 [See: ../timer/st,stih407-lpc for Clocksource options]
12 - compatible : Should be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
24 - st,syscfg : Phandle to syscfg node used to enable watchdog and configure
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H A Dxlnx,versal-wwdt.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/xlnx,versal-wwdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neeli Srinivas <srinivas.neeli@amd.com>
16 predefined window periods of time. This means a period that is not
18 restarted within the open window time. If software tries to restart
19 WWDT outside of the open window time period, it generates a reset.
22 - $ref: watchdog.yaml#
27 - xlnx,versal-wwdt
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H A Drealtek,otto-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/realtek,otto-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sander Vanheule <sander@svanheule.net>
16 interrupt, although the phase 2 interrupt will occur with the system reset.
17 - Phase 1: During this phase, the WDT can be pinged to reset the timeout.
18 - Phase 2: Starts after phase 1 has timed out, and only serves to give the
19 system some time to clean up, or notify others that it's going to reset.
20 During this phase, pinging the WDT has no effect, and a reset is
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H A Datmel,sama5d4-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/atmel,sama5d4-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eugen Hristev <eugen.hristev@microchip.com>
13 - $ref: watchdog.yaml#
18 - enum:
19 - atmel,sama5d4-wdt
20 - microchip,sam9x60-wdt
21 - microchip,sama7g5-wdt
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/linux/Documentation/devicetree/bindings/input/
H A Dinput.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Torokhov <dmitry.torokhov@gmail.com>
21 $ref: /schemas/types.yaml#/definitions/uint32-array
34 linux,input-type:
37 - 1 # EV_KEY
38 - 2 # EV_REL
39 - 3 # EV_ABS
40 - 5 # EV_SW
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/linux/arch/powerpc/platforms/chrp/
H A Dtime.c1 // SPDX-License-Identifier: GPL-2.0
7 * Copied and modified from arch/i386/kernel/time.c
17 #include <linux/time.h>
29 #include <asm/time.h>
49 rtcs = of_find_compatible_node(NULL, "rtc", "ds1385-rtc"); in chrp_time_init()
84 * Set the hardware clock. -- Cort
97 save_freq_select = chrp_cmos_clock_read(RTC_FREQ_SELECT); /* stop and reset prescaler */ in chrp_set_rtc_time()
118 * battery and quartz) will not reset the oscillator and will not in chrp_set_rtc_time()
121 * sheets anyway ... -- Markus Kuhn in chrp_set_rtc_time()
132 unsigned int year, mon, day, hour, min, sec; in chrp_get_rtc_time() local
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/linux/drivers/scsi/fnic/
H A Dfnic_trace.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/time.h>
46 * fnic_trace_get_buf - Give buffer pointer to user to fill up trace information
93 * fnic_get_trace_data - Copy trace buffer to a memory file
129 sprint_symbol(str, tbp->fnaddr.low); in fnic_get_trace_data()
130 jiffies_to_timespec64(tbp->timestamp.low, &val); in fnic_get_trace_data()
132 sprint_symbol(str, tbp->fnaddr.val); in fnic_get_trace_data()
133 jiffies_to_timespec64(tbp->timestamp.val, &val); in fnic_get_trace_data()
139 len += scnprintf(fnic_dbgfs_prt->buffer + len, in fnic_get_trace_data()
140 (trace_max_pages * PAGE_SIZE * 3) - len, in fnic_get_trace_data()
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/linux/Documentation/devicetree/bindings/sound/
H A Dsamsung-i2s.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/samsung-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - $ref: dai-common.yaml#
19 samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
21 samsung,s5pv210-i2s: for 8/16/24bit multichannel (5.1) I2S with
22 secondary FIFO, s/w reset control and internal mux for root clock
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/linux/Documentation/networking/dsa/
H A Dsja1105.rst8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
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/linux/drivers/watchdog/
H A Di6300esb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * based on i810-tco.c which is in turn based on softdog.c
12 * 6300ESB chip : document number 300641-004
49 #define ESB_TIMER1_REG(w) ((w)->base + 0x00)/* Timer1 value after each reset */
50 #define ESB_TIMER2_REG(w) ((w)->base + 0x04)/* Timer2 value after each reset */
51 #define ESB_GINTSR_REG(w) ((w)->base + 0x08)/* General Interrupt Status Reg */
52 #define ESB_RELOAD_REG(w) ((w)->base + 0x0c)/* Reload register */
69 #define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
70 #define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
73 /* 30 sec default heartbeat (1 < heartbeat < 2*1023) */
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H A Dpcwd_pci.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Berkshire PCI-PC Watchdog Card Driver
5 * (c) Copyright 2003-2007 Wim Van Sebroeck <wim@iguana.be>.
16 * provided "AS-IS" and at no charge.
36 #include <linux/errno.h> /* For the -ENODEV/... values */
46 #include <linux/ioport.h> /* For io-port access */
53 #define WATCHDOG_DRIVER_NAME "PCI-PC Watchdog"
68 * PCI-PC Watchdog card.
76 #define WD_PCI_R2DS 0x40 /* Relay 2 Disable Temperature-trip /
77 reset */
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H A Dat91sam9_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
41 readl_relaxed((wdt)->base + (field))
43 writel_relaxed((val), (wdt)->base + (field))
52 #define secs_to_ticks(s) ((s) ? (((s) << 8) - 1) : 0)
101 pr_crit("at91sam9 WDT software reset\n"); in wdt_interrupt()
123 if (time_before(jiffies, wdt->next_heartbeat) || in at91_ping()
124 !watchdog_active(&wdt->wdd)) { in at91_ping()
126 mod_timer(&wdt->timer, jiffies + wdt->heartbeat); in at91_ping()
128 pr_crit("I will reset your machine !\n"); in at91_ping()
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H A Dsc520_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * any of this software. This material is provided "AS-IS" in
13 * 9/27 - 2001 [Initial release]
16 * - Fixed formatting
17 * - Removed debug printks
18 * - Fixed SMP built kernel deadlock
19 * - Switched to private locks not lock_kernel
20 * - Used ioremap/writew/readw
21 * - Added NOWAYOUT support
22 * 4/12 - 2002 Changes by Rob Radez <rob@osinvestor.com>
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H A Dib700wdt.c1 // SPDX-License-Identifier: GPL-2.0+
10 * (c) Copyright 2000-2001 Marek Michalkiewicz <marekm@linux.org.pl>
20 * "AS-IS" and at no charge.
24 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
58 * The function of the watchdog timer is to reset the system
60 * watchdog timer and allow the system to reset, write I/O port 0443H.
78 * Level Value Time/sec | Level Value Time/sec
94 #define WATCHDOG_TIMEOUT 30 /* 30 seconds +/- 20% */
114 int wd_margin = 15 - ((timeout + 1) / 2); in ibwdt_ping()
134 return -EINVAL; in ibwdt_set_heartbeat()
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/linux/drivers/rtc/
H A Drtc-s32g.c1 // SPDX-License-Identifier: GPL-2.0-or-later
84 status = readl(priv->rtc_base + RTCS_OFFSET); in s32g_rtc_handler()
87 writel(0x0, priv->rtc_base + APIVAL_OFFSET); in s32g_rtc_handler()
88 writel(status | RTCS_APIF, priv->rtc_base + RTCS_OFFSET); in s32g_rtc_handler()
91 rtc_update_irq(priv->rdev, 1, RTC_IRQF | RTC_AF); in s32g_rtc_handler()
97 * The function is not really getting time from the RTC since the S32G RTC
98 * has several limitations. Thus, to setup alarm use system time.
104 time64_t sec; in s32g_rtc_read_time() local
107 priv->sleep_sec, &sec)) in s32g_rtc_read_time()
108 return -ERANGE; in s32g_rtc_read_time()
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H A Drtc-renesas-rtca3.c1 // SPDX-License-Identifier: GPL-2.0
3 * On-Chip RTC Support available on RZ/G3S SoC
19 #include <linux/reset.h>
93 * enum rtca3_alrm_set_step - RTCA3 alarm set steps
105 * struct rtca3_ppb_per_cycle - PPB per cycle
115 * struct rtca3_priv - RTCA3 private data structure
118 * @rstc: reset control
140 tmp = readb(priv->base + off); in rtca3_byte_update_bits()
143 writeb(tmp, priv->base + off); in rtca3_byte_update_bits()
150 val = readb(priv->base + RTCA3_RSR); in rtca3_alarm_handler_helper()
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/linux/drivers/block/drbd/
H A Ddrbd_proc.c1 // SPDX-License-Identifier: GPL-2.0-only
7 Copyright (C) 2001-2008, LINBIT Information Technologies GmbH.
8 Copyright (C) 1999-2008, Philipp Reisner <philipp.reisner@linbit.com>.
9 Copyright (C) 2002-2008, Lars Ellenberg <lars.ellenberg@linbit.com>.
28 /* v is in kB/sec. We don't expect TiByte/sec yet. */ in seq_printf_with_thousands_grouping()
44 /* this is to break it at compile time when we change that, in case we in drbd_get_syncer_progress()
46 typecheck(unsigned long, device->rs_total); in drbd_get_syncer_progress()
47 *rs_total = device->rs_total; in drbd_get_syncer_progress()
54 *bits_left = device->ov_left; in drbd_get_syncer_progress()
56 *bits_left = drbd_bm_total_weight(device) - device->rs_failed; in drbd_get_syncer_progress()
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/linux/Documentation/bpf/
H A Dprog_cgroup_sockopt.rst1 .. SPDX-License-Identifier: GPL-2.0
10 * ``BPF_CGROUP_GETSOCKOPT`` - called every time process executes ``getsockopt``
12 * ``BPF_CGROUP_SETSOCKOPT`` - called every time process executes ``setsockopt``
26 If BPF program sets ``optlen`` to -1, the control will be returned
30 Note, that ``optlen`` can not be increased beyond the user-supplied
31 value. It can only be decreased or set to -1. Any other value will
35 -----------
37 * ``0`` - reject the syscall, ``EPERM`` will be returned to the userspace.
38 * ``1`` - success, continue with next BPF program in the cgroup chain.
46 the values above, adjust ``optlen`` and reset ``retval`` to 0. If ``optlen``
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/linux/drivers/mtd/nand/raw/
H A Dmtk_nand.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include <linux/dma-mapping.h>
19 #include <linux/mtd/nand-ecc-mtk.h>
89 #define MTK_NAME "mtk-nand"
112 u32 sec; member
185 return (u8 *)p + i * chip->ecc.size; in data_ptr()
197 if (i < mtk_nand->bad_mark.sec) in oob_ptr()
198 poi = chip->oob_poi + (i + 1) * mtk_nand->fdm.reg_size; in oob_ptr()
199 else if (i == mtk_nand->bad_mark.sec) in oob_ptr()
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/linux/drivers/input/misc/
H A Datc260x-onkey.c1 // SPDX-License-Identifier: GPL-2.0+
80 reg_bm = onkey->params->long_int_pnd_bm | in atc2603x_onkey_hw_init()
81 onkey->params->short_int_pnd_bm | in atc2603x_onkey_hw_init()
82 onkey->params->kdwn_int_pnd_bm | in atc2603x_onkey_hw_init()
83 onkey->params->press_int_en_bm | in atc2603x_onkey_hw_init()
84 onkey->params->kdwn_int_en_bm; in atc2603x_onkey_hw_init()
87 reg_bm |= onkey->params->press_time_bm; in atc2603x_onkey_hw_init()
90 reg_bm |= onkey->params->reset_en_bm; in atc2603x_onkey_hw_init()
92 reg_bm |= onkey->params->reset_en_bm | in atc2603x_onkey_hw_init()
93 onkey->params->reset_time_bm; in atc2603x_onkey_hw_init()
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/linux/drivers/usb/chipidea/
H A Dotg_fsm.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/usb/otg-fsm.h>
14 * A-DEVICE timing constants
21 * Table 4-1: Electrical Characteristics
22 * ->DC Electrical Timing
28 /* Wait for B-Connect */
31 * and 30000 ms, section 5.5, Table 5-1
33 /* A-Idle to B-Disconnect */
35 * TA_AIDL_BDIS: section 5.5, Table 5-1
37 /* B-Idle to A-Disconnect */
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