1 // SPDX-License-Identifier: GPL-2.0-or-later
84 	status = readl(priv->rtc_base + RTCS_OFFSET);  in s32g_rtc_handler()
87 		writel(0x0, priv->rtc_base + APIVAL_OFFSET);  in s32g_rtc_handler()
88 		writel(status | RTCS_APIF, priv->rtc_base + RTCS_OFFSET);  in s32g_rtc_handler()
91 	rtc_update_irq(priv->rdev, 1, RTC_IRQF | RTC_AF);  in s32g_rtc_handler()
97  * The function is not really getting time from the RTC since the S32G RTC
98  * has several limitations. Thus, to setup alarm use system time.
104 	time64_t sec;  in s32g_rtc_read_time()  local
107 			       priv->sleep_sec, &sec))  in s32g_rtc_read_time()
108 		return -ERANGE;  in s32g_rtc_read_time()
110 	rtc_time64_to_tm(sec, tm);  in s32g_rtc_read_time()
120 	rtcc = readl(priv->rtc_base + RTCC_OFFSET);  in s32g_rtc_read_alarm()
121 	rtcs = readl(priv->rtc_base + RTCS_OFFSET);  in s32g_rtc_read_alarm()
123 	alrm->enabled = rtcc & RTCC_APIIE;  in s32g_rtc_read_alarm()
124 	if (alrm->enabled)  in s32g_rtc_read_alarm()
125 		alrm->pending = !(rtcs & RTCS_APIF);  in s32g_rtc_read_alarm()
138 	rtcc = readl(priv->rtc_base + RTCC_OFFSET);  in s32g_rtc_alarm_irq_enable()
140 	writel(rtcc, priv->rtc_base + RTCC_OFFSET);  in s32g_rtc_alarm_irq_enable()
154 	alrm_time = rtc_tm_to_time64(&alrm->time);  in s32g_rtc_set_alarm()
155 	t_offset = alrm_time - ktime_get_real_seconds() - priv->sleep_sec;  in s32g_rtc_set_alarm()
157 		return -ERANGE;  in s32g_rtc_set_alarm()
159 	cycles = t_offset * priv->rtc_hz;  in s32g_rtc_set_alarm()
161 		return -ERANGE;  in s32g_rtc_set_alarm()
163 	/* APIVAL could have been reset from the IRQ handler.  in s32g_rtc_set_alarm()
167 				0, RTC_SYNCH_TIMEOUT, false, priv->rtc_base + RTCS_OFFSET);  in s32g_rtc_set_alarm()
171 	writel(cycles, priv->rtc_base + APIVAL_OFFSET);  in s32g_rtc_set_alarm()
174 				0, RTC_SYNCH_TIMEOUT, false, priv->rtc_base + RTCS_OFFSET);  in s32g_rtc_set_alarm()
178  * Disable the 32-bit free running counter.
184 	u32 rtcc = readl(priv->rtc_base + RTCC_OFFSET);  in s32g_rtc_disable()
187 	writel(rtcc, priv->rtc_base + RTCC_OFFSET);  in s32g_rtc_disable()
192 	u32 rtcc = readl(priv->rtc_base + RTCC_OFFSET);  in s32g_rtc_enable()
195 	writel(rtcc, priv->rtc_base + RTCC_OFFSET);  in s32g_rtc_enable()
202 	rtcc = FIELD_PREP(RTCC_CLKSEL_MASK, priv->clk_src_idx);  in rtc_clk_src_setup()
204 	switch (priv->rtc_data->clk_div) {  in rtc_clk_src_setup()
218 		return -EINVAL;  in rtc_clk_src_setup()
227 	writel(rtcc, priv->rtc_base + RTCC_OFFSET);  in rtc_clk_src_setup()
245 	priv->ipg = devm_clk_get_enabled(dev, "ipg");  in rtc_clk_dts_setup()
246 	if (IS_ERR(priv->ipg))  in rtc_clk_dts_setup()
247 		return dev_err_probe(dev, PTR_ERR(priv->ipg),  in rtc_clk_dts_setup()
251 		if (priv->rtc_data->reserved_clk_mask & BIT(i))  in rtc_clk_dts_setup()
252 			return -EOPNOTSUPP;  in rtc_clk_dts_setup()
254 		priv->clk_src = devm_clk_get_enabled(dev, rtc_clk_src[i]);  in rtc_clk_dts_setup()
255 		if (!IS_ERR(priv->clk_src)) {  in rtc_clk_dts_setup()
256 			priv->clk_src_idx = i;  in rtc_clk_dts_setup()
261 	if (IS_ERR(priv->clk_src))  in rtc_clk_dts_setup()
262 		return dev_err_probe(dev, PTR_ERR(priv->clk_src),  in rtc_clk_dts_setup()
270 	struct device *dev = &pdev->dev;  in s32g_rtc_probe()
277 		return -ENOMEM;  in s32g_rtc_probe()
279 	priv->rtc_data = of_device_get_match_data(dev);  in s32g_rtc_probe()
280 	if (!priv->rtc_data)  in s32g_rtc_probe()
281 		return -ENODEV;  in s32g_rtc_probe()
283 	priv->rtc_base = devm_platform_ioremap_resource(pdev, 0);  in s32g_rtc_probe()
284 	if (IS_ERR(priv->rtc_base))  in s32g_rtc_probe()
285 		return PTR_ERR(priv->rtc_base);  in s32g_rtc_probe()
293 	priv->rdev = devm_rtc_allocate_device(dev);  in s32g_rtc_probe()
294 	if (IS_ERR(priv->rdev))  in s32g_rtc_probe()
295 		return PTR_ERR(priv->rdev);  in s32g_rtc_probe()
301 	priv->irq = platform_get_irq(pdev, 0);  in s32g_rtc_probe()
302 	if (priv->irq < 0) {  in s32g_rtc_probe()
303 		ret = priv->irq;  in s32g_rtc_probe()
307 	rtc_hz = clk_get_rate(priv->clk_src);  in s32g_rtc_probe()
310 		ret = -EINVAL;  in s32g_rtc_probe()
314 	priv->rtc_hz = DIV_ROUND_UP(rtc_hz, priv->rtc_data->clk_div);  in s32g_rtc_probe()
317 	priv->rdev->ops = &rtc_ops;  in s32g_rtc_probe()
319 	ret = devm_request_irq(dev, priv->irq,  in s32g_rtc_probe()
323 			priv->irq, ret);  in s32g_rtc_probe()
327 	ret = devm_rtc_register_device(priv->rdev);  in s32g_rtc_probe()
341 	u32 apival = readl(priv->rtc_base + APIVAL_OFFSET);  in s32g_rtc_suspend()
343 	if (check_add_overflow(priv->sleep_sec, div64_u64(apival, priv->rtc_hz),  in s32g_rtc_suspend()
344 			       &priv->sleep_sec)) {  in s32g_rtc_suspend()
346 		priv->sleep_sec = 0;  in s32g_rtc_suspend()
356 	/* The transition from resume to run is a reset event.  in s32g_rtc_resume()
357 	 * This leads to the RTC registers being reset after resume from  in s32g_rtc_resume()
366 	{ .compatible = "nxp,s32g2-rtc", .data = &rtc_s32g2_data },
375 		.name = "s32g-rtc",