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/freebsd/sys/dev/ice/
H A Dice_hw_autogen.h1 /* SPDX-License-Identifier: BSD-3-Clause */
5 * Redistribution and use in source and binary forms, with or without
8 * 1. Redistributions of source code must retain the above copyright notice,
37 #define PRTMAC_CTL_TX_PAUSE_ENABLE_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_TX_PAUSE_ENABLE : E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE)
38 #define PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_S_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_S : E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_S)
39 #define PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_M : E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_M)
40 #define PRTMAC_CTL_RX_PAUSE_ENABLE_BY_MAC(hw) ((hw)->mac_typ
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,qca8k-nsscc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
10 - Bjorn Andersson <andersson@kernel.org>
11 - Luo Jie <quic_luoj@quicinc.com>
18 include/dt-bindings/clock/qcom,qca8k-nsscc.h
19 include/dt-bindings/reset/qcom,qca8k-nsscc.h
24 - const: qcom,qca8084-nsscc
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H A Dqcom,sm8450-gpucc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller on SM8450
10 - Konrad Dybcio <konradybcio@kernel.org>
17 include/dt-bindings/clock/qcom,sm4450-gpucc.h
18 include/dt-bindings/clock/qcom,sm8450-gpucc.h
19 include/dt-bindings/clock/qcom,sm8550-gpucc.h
20 include/dt-bindings/reset/qcom,sm8450-gpucc.h
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H A Dqcom,sm4450-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SM4450
10 - Ajit Pandey <quic_ajipan@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
17 See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
21 const: qcom,sm4450-dispcc
28 - description: Board XO source
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H A Dstericsson,u8500-clks.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 (U8500) clocks
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Linus Walleij <linus.walleij@linaro.org>
14 DB8500 digital baseband system-on-chip and its siblings such as
16 itself, not off-chip clocks. There are four different on-chip
17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
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H A Dqcom,ipq5018-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ5018
10 - Sricharan Ramabadhran <quic_srichara@quicinc.com>
17 include/dt-bindings/clock/qcom,ipq5018-gcc.h
18 include/dt-bindings/reset/qcom,ipq5018-gcc.h
22 const: qcom,gcc-ipq5018
26 - description: Board XO source
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H A Dqcom,ipq9574-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ9574
10 - Bjorn Andersson <andersson@kernel.org>
11 - Anusha Rao <quic_anusha@quicinc.com>
18 include/dt-bindings/clock/qcom,ipq9574-gcc.h
19 include/dt-bindings/reset/qcom,ipq9574-gcc.h
23 const: qcom,ipq9574-gcc
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H A Dqcom,sc7180-gpucc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7180-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller Binding for SC7180
10 - Taniya Das <tdas@codeaurora.org>
16 See also dt-bindings/clock/qcom,gpucc-sc7180.h.
20 const: qcom,sc7180-gpucc
24 - description: Board XO source
25 - description: GPLL0 main branch source
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H A Dqcom,sdm845-gpucc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sdm845-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller Binding for SDM845
10 - Taniya Das <tdas@codeaurora.org>
16 See also dt-bindings/clock/qcom,gpucc-sdm845.h.
20 const: qcom,sdm845-gpucc
24 - description: Board XO source
25 - description: GPLL0 main branch source
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H A Dqcom,sc7280-camcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7280-camc
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H A Dqcom,gpucc-sm8350.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller on SM8350
10 - Robert Foss <robert.foss@linaro.org>
16 See also:: include/dt-bindings/clock/qcom,gpucc-sm8350.h
21 - qcom,sm8350-gpucc
25 - description: Board XO source
26 - description: GPLL0 main branch source
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H A Dqcom,camcc-sm8250.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,camcc-sm825
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/freebsd/sys/contrib/device-tree/Bindings/power/reset/
H A Dgpio-restart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpi
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H A Dgpio-restart.txt4 This binding supports level and edge triggered reset. At driver load
6 handler. If the optional properties 'open-source' is not found, the GPIO line
12 triggering a level triggered reset condition. This will also cause an
13 inactive->active edge condition, triggering positive edge triggered
14 reset. After a delay specified by active-delay, the GPIO is set to
15 inactive, thus causing an active->inactive edge, triggering negative edge
16 triggered reset. After a delay specified by inactive-delay, the GPIO
17 is driven active again. After a delay specified by wait-delay, the
21 - compatible : should be "gpio-restart".
22 - gpios : The GPIO to set high/low, see "gpios property" in
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/freebsd/sys/dev/mlx4/mlx4_core/
H A Dmlx4_reset.c8 * COPYING in the main directory of this source tree, or the
11 * Redistribution and use in source and binary forms, with or
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
44 void __iomem *reset; in mlx4_reset() local
65 * Reset the chip. This is somewhat ugly because we have to in mlx4_reset()
66 * save off the PCI header before reset and then restore it in mlx4_reset()
74 err = -ENOMEM; in mlx4_reset()
79 pcie_cap = pci_pcie_cap(dev->persist->pdev); in mlx4_reset()
84 if (pci_read_config_dword(dev->persist->pdev, i * 4, in mlx4_reset()
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pci
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/freebsd/usr.bin/bmake/tests/
H A DREADME6 ----------------------------------------------------------------------------
10 The tests are invoked via the test.sh script or prove(1) from p5-Test-Harness.
16 tests are executed by cd-ing into that directory and invoking make. The
21 ./shell/builtin/ - directory with test stuff
22 /tmp/make.${USER}/shell/builtin - actual test directory
23 /tmp/make.${USER}/shell/builtin.OUTPUT - output files
27 setup - Set up the test environment by creating the test directory
31 run - Run the test and produce the output into the output
34 show - Show the result files on the screen.
36 compare - Compare the results in the output directory with those
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/freebsd/sys/dev/iavf/
H A Diavf_register.h1 /* SPDX-License-Identifier: BSD-3-Clause */
5 * Redistribution and use in source and binary forms, with or without
8 * 1. Redistributions of source code must retain the above copyright notice,
35 #define IAVF_VF_ARQBAH1 0x00006000 /* Reset: EMPR */
36 #define IAVF_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */
37 #define IAVF_VF_ARQH1 0x00007400 /* Reset: EMPR */
40 #define IAVF_VF_ARQLEN1 0x00008000 /* Reset: EMPR */
49 #define IAVF_VF_ARQT1 0x00007000 /* Reset: EMPR */
50 #define IAVF_VF_ATQBAH1 0x00007800 /* Reset: EMPR */
51 #define IAVF_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */
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/freebsd/sys/arm/freescale/imx/
H A Dimx_machdep.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
7 * Redistribution and use in source and binary forms, with or without
10 * 1. Redistributions of source code must retain the above copyright
52 &last_reset_status, 0, "Last reset status register");
55 "unknown", 0, "Last reset reason");
59 * cpu_reset() because the watchdog is the only way for software to reset the
78 * If the watchdog hardware has been set up to trigger an external reset in imx_wdog_cpu_reset()
79 * signal on watchdog timeout, then we do software-requested rebooting in imx_wdog_cpu_reset()
80 * the same way, by asserting the external reset signal. in imx_wdog_cpu_reset()
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H A Dimx_wdogreg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
9 * Redistribution and use in source and binary forms, with or without
12 * 1. Redistributions of source code must retain the above copyright
37 #define WDOG_CR_WDA (1u << 5) /* Don't assert ext reset */
38 #define WDOG_CR_SRS (1u << 4) /* Don't assert soft reset */
39 #define WDOG_CR_WDT (1u << 3) /* Assert ext reset on timeout */
48 #define WDOG_RSR_REG 0x04 /* Reset Status Register */
49 #define WDOG_RSR_POR (1u << 4) /* Due to Power-On Reset */
50 #define WDOG_RSR_TOUT (1u << 1) /* Due WDog timeout reset */
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/freebsd/sys/contrib/device-tree/Bindings/input/
H A Dnvidia,tegra20-kbc.txt7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
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/freebsd/contrib/unbound/daemon/
H A Dstats.h2 * daemon/stats.h - collect runtime performance indicators.
6 * This software is open source.
8 * Redistribution and use in source and binary forms, with or without
12 * Redistributions of source code must retain the above copyright notice,
78 * @param reset: if stats can be reset.
81 struct ub_stats_info* s, int reset);
88 * @param reset: if true, depending on config stats are reset.
89 * if false, statistics are not reset.
92 int reset);
97 * @param reset: if true, depending on config stats are reset.
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/freebsd/share/man/man4/man4.arm/
H A Dimx_wdog.45 .\" Redistribution and use in source and binary forms, with or without
9 .\" 1. Redistributions of source code must retain the above copyright
36 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
53 0.5 to 128 seconds, in half-second increments.
55 timeout period can be changed to any valid non-zero value.
57 At power-on, a special 16-second
58 .Sq power-down timer
61 external hardware that causes the system to reset or power-down.
62 The power-down timer is often reset by the boot loader (typically U-Boot).
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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dnvidia,tegra124-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
20 - description: NVIDIA Tegra124
21 const: nvidia,tegra124-xusb
23 - description: NVIDIA Tegra132
25 - const: nvidia,tegra132-xusb
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/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dhisilicon,hi3660-reset.txt1 Hisilicon System Reset Controller
4 Please also refer to reset.txt in this directory for common reset
7 The reset controller registers are part of the system-ctl block on
11 - compatible: should be one of the following:
12 "hisilicon,hi3660-reset" for HI3660
13 "hisilicon,hi3670-reset", "hisilicon,hi3660-reset" for HI3670
14 - hisi,rst-syscon: phandle of the reset's syscon.
15 - #reset-cells : Specifies the number of cells needed to encode a
16 reset source. The type shall be a <u32> and the value shall be 2.
18 Cell #1 : offset of the reset assert control
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