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/titanic_51/usr/src/uts/common/io/fibre-channel/fca/qlc/
H A Dqlc.conf17 # information: Portions Copyright [yyyy] [name of copyright owner]
34 # Copyright (C) QLogic Corporation 1998-2010. All rights reserved.
50 # enable-adapter-hard-loop-ID=0;
52 # adapter-hard-loop-ID=0;
55 # enable-adapte
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dst,stpmic1.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - pascal Paillet <p.paillet@foss.st.com>
24 "#interrupt-cells":
27 interrupt-controller: true
36 const: st,stpmic1-onkey
40 - description: onkey-falling, happens when onkey is pressed. IT_PONKEY_F of pmic
41 - description: onkey-rising, happens when onkey is released. IT_PONKEY_R of pmic
43 interrupt-names:
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H A Drohm,bd71847-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd71847-pmi
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H A Drohm,bd71837-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd71837-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
13 BD71837MWV is programmable Power Management ICs for powering single-core,
14 dual-core, and quad-core SoCs such as NXP-i.MX 8M. It is optimized for low
18 …/www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-applica…
35 clock-names:
38 "#clock-cells":
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/titanic_51/usr/src/man/man9f/
H A Dusb_reset_device.9f5 .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner]
7 .SH NAME
8 usb_reset_device \- reset a USB device according to the reset_level.
42 The level to which the device is reset. See below for a list of valid
50 hardware reset for a \fBUSB\fR device, which may be required in some situations
64 \fBRAM\fR and initiate a hardware reset in order to activate the new firmware.
76 The default reset level. The device is reset and any error status is cleared.
78 reinitialized in the driver. The current driver remains attached. This reset
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H A Dscsi_reset_notify.9f6 .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner]
8 .SH NAME
9 scsi_reset_notify \- notify target driver of bus resets
50 A pointer to the target driver's reset notification function.
66 to be notified of a bus reset. The bus reset could be issued by the transport
79 Register \fIcallback\fR as the reset notification function for the target
89 Cancel the reset notification request.
95 reset notification by checking the \fBreset-notificatio
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H A Dscsi_reset.9f5 .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner]
7 .SH NAME
8 scsi_reset \- reset a SCSI bus or target
39 The level of reset required.
45 The \fBscsi_reset()\fR function asks the host adapter driver to reset the
47 \fIlevel\fR equals \fBRESET_ALL\fR, the \fBSCSI\fR bus is reset. If it equals
48 \fBRESET_TARGET\fR, \fIap\fR is used to determine the target to be reset. If it
50 reset.
54 the \fBLOGICAL UNIT RESET\f
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H A Dusb_pipe_reset.9f5 .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner]
7 .SH NAME
8 usb_pipe_reset \- Abort queued requests from a USB pipe and reset the pipe
41 Handle of the pipe to reset. Cannot be the handle to the default control pipe.
75 Call \fBusb_pipe_reset()\fR to reset a pipe which is in an error state, or to
80 A pipe can be reset automatically when requests sent to the pipe have the
94 1. Any polling activity is stopped if the pipe being reset is an interrupt or
96 .in -2
101 .in -
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/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
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/freebsd/usr.sbin/devctl/
H A Ddevctl.828 .Sh NAME
72 .Cm reset
86 consists of a single command followed by command-specific arguments.
92 may be specified either as the name of an existing device or as a
93 bus-specific address.
98 .Bl -tag -width indent
100 Force the kernel to re-probe the device.
119 but the device will retain its current name.
127 Note that this can re-enable a device disabled at boot time via a
153 Clear a previously-forced driver name so that the device is able to use any
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/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-g12.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-g12a-power.h>
10 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
11 #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
14 tdmif_a: audio-controller-0 {
15 compatible = "amlogic,axg-tdm-iface";
16 #sound-dai-cells = <0>;
17 sound-name-prefix = "TDM_A";
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H A Dmeson-sm1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-sm1-power.h>
10 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
11 #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
16 tdmif_a: audio-controller-0 {
17 compatible = "amlogic,axg-tdm-iface";
18 #sound-dai-cells = <0>;
19 sound-name-prefix = "TDM_A";
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/titanic_51/usr/src/man/man9e/
H A Dtran_reset.9e5 .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner]
7 .SH NAME
8 tran_reset \- reset a SCSI bus or target
39 The level of reset required.
51 \fBtran_reset()\fR must reset either the \fBSCSI\fR bus, a \fBSCSI\fR target
62 Reset the \fBSCSI\fR bus.
71 Reset the target specified by \fIap\fR.
80 Reset the logical unit specified by \fIap\fR.
87 was successfully reset t
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dhisilicon-hix5hd2-gmac.txt4 - compatible: should contain one of the following SoC strings:
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
13 - reg: specifies base physical address(s) and size of the device registers.
16 - interrupts: should contain the MAC interrupt.
17 - #address-cells: must be <1>.
18 - #size-cells: must be <0>.
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H A Dsnps,dwc-qos-ethernet.txt7 IP block. The IP supports multiple options for bus type, clocking and reset
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqo
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/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-385-clearfog-gtr.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
9 SERDES mapping -
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
12 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
14 4. mini PCIe CON2 - PCIe2
17 USB 2.0 mapping -
18 0. USB 2.0 - 0 USB pins header CON12
19 1. USB 2.0 - 1 mini PCIe CON2
20 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
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/freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/LogicalView/Core/
H A DLVSupport.h1 //===-- LVSupport.h ---------------------------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
46 void reset(T Idx) { Bits[static_cast<unsigned>(Idx)] = 0; } in reset() function
50 // Generate get, set and reset 'bool' functions for LVProperties instances.
51 // FAMILY: instance name.
58 void reset##FIELD() { FAMILY.reset(ENUM::FIELD); }
66 void reset##FIELD() { FAMILY.reset(ENUM::FIELD); }
75 void reset##FIELD() { FAMILY.reset(ENUM::FIELD); }
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/freebsd/contrib/llvm-project/llvm/lib/ObjectYAML/
H A DWasmYAML.cpp1 //===- WasmYAML.cpp - Wasm YAMLIO implementation --------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
25 // http://llvm.org/docs/CodingStandards.html#provide-a-virtual-method-anchor-for-classes-in-headers
54 IO.mapRequired("Name", Section.Name); in sectionMapping()
66 IO.mapRequired("Name", Section.Name); in sectionMapping()
74 IO.mapRequired("Name", Section.Name); in sectionMapping()
84 IO.mapRequired("Name", Section.Name); in sectionMapping()
92 IO.mapRequired("Name", Section.Name); in sectionMapping()
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/freebsd/sys/dev/mlx5/mlx5_core/
H A Dmlx5_health.c1 /*-
2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved.
60 "Enable firmware reset");
73 ret = -mlx5_vsc_lock(dev); in lock_sem_sw_reset()
79 ret = -mlx5_vsc_lock_addr_space(dev, MLX5_SEMAPHORE_SW_RESET); in lock_sem_sw_reset()
81 if (ret == -EBUSY) in lock_sem_sw_reset()
83 "SW reset FW semaphore already locked, another function will handle the reset\n"); in lock_sem_sw_reset()
86 "SW reset semaphore lock return %d\n", ret); in lock_sem_sw_reset()
100 ret = -mlx5_vsc_lock(dev); in unlock_sem_sw_reset()
106 ret = -mlx5_vsc_unlock_addr_space(dev, MLX5_SEMAPHORE_SW_RESET); in unlock_sem_sw_reset()
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/freebsd/contrib/llvm-project/lldb/source/API/
H A DSBListener.cpp1 //===-- SBListener.cpp ----------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
25 SBListener::SBListener(const char *name) in SBListener() argument
26 : m_opaque_sp(Listener::MakeListener(name)) { in SBListener()
27 LLDB_INSTRUMENT_VA(this, name); in SBListener()
51 return this->operator bool(); in IsValid()
64 m_opaque_sp->AddEvent(event_sp); in AddEvent()
71 m_opaque_sp->Clear(); in Clear()
84 return m_opaque_sp->StartListeningForEventSpec( in StartListeningForEventClass()
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/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dreset.txt1 = Reset Signal Device Tree Bindings =
3 This binding is intended to represent the hardware reset signals present
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-iota2-lumpy.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "ysoft,imx8mp-iota2-lumpy", "fsl,imx8mp";
15 compatible = "pwm-beeper";
20 stdout-path = &uart2;
23 gpio_keys: gpio-keys {
24 compatible = "gpio-keys";
25 pinctrl-0 = <&pinctrl_gpio_keys>;
26 pinctrl-names = "default";
28 button-reset {
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/freebsd/contrib/ncurses/man/
H A Dtput.13 .\" Copyright 2018-2023,2024 Thomas E. Dickey *
4 .\" Copyright 1998-2016,2017 Free Software Foundation, Inc. *
25 .\" Except as contained in this notice, the name(s) of the above copyright *
32 .TH @TPUT@ 1 2024-04-20 "ncurses @NCURSES_MAJOR@.@NCURSES_MINOR@" "User commands"
49 .SH NAME
50 \fB\%@TPUT@\fP \-
53 \fB@TPUT@\fP [\fB\-T\fP \fIterminal-type\fP]
54 {\fIcap-code\fP [\fIparameter\fP .\|.\|.\&]} .\|.\|.
56 \fB@TPUT@\fP [\fB\-T\fP \fIterminal-type\fP] [\fB\-x\fP] \fBclear\fP
58 \fB@TPUT@\fP [\fB\-T\fP \fIterminal-type\fP] \fBinit\fP
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/freebsd/bin/pax/
H A Dtables.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
19 * 3. Neither the name of the University nor the names of its contributors
49 #define A_TAB_SZ 317 /* ftree dir access time reset table */
57 char *name; /* name of first file seen with this ino/dev */ member
65 * Archive write update file time table (the -u, -C flag), hashed by filename.
67 * file time (mod time) and the file name length (for a quick check) are
69 * with -u, the mtime for every node in the archive must always be available
76 int namelen; /* file name length */
83 * Interactive rename table (-i flag), hashed by orig filename.
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
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