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/linux/drivers/accel/habanalabs/include/gaudi2/
H A Dgaudi2_async_ids_map_extended.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2018-2022 HabanaLabs, Ltd.
9 ** This is an auto-generated file **
27 int reset; member
28 char name[64]; member
32 { .fc_id = 0, .cpu_id = 0, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
33 .name = "" },
34 { .fc_id = 1, .cpu_id = 1, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
35 .name = "" },
36 { .fc_id = 2, .cpu_id = 2, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
[all …]
/linux/drivers/pmdomain/ti/
H A Domap_prm.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Tero Kristo <t-kristo@ti.com>
19 #include <linux/reset-controller.h>
22 #include <linux/platform_data/ti-prm.h>
33 unsigned long statechange:1; /* Optional low-power state change */
55 const char *name; member
139 { .rst = -1 },
145 { .rst = -1 },
152 { .rst = -1 },
[all …]
/linux/drivers/clk/bcm/
H A Dclk-bcm63268-timer.c1 // SPDX-License-Identifier: GPL-2.0
3 * BCM63268 Timer Clock and Reset Controller Driver
8 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/bcm63268-clock.h>
31 const char * const name; member
37 .name = "ephy1",
40 .name = "ephy2",
43 .name = "ephy3",
46 .name = "gphy1",
[all …]
/linux/drivers/gpio/
H A Dgpiolib-of.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2007-2008 MontaVista Software, Inc.
26 #include "gpiolib-of.h"
29 * This is Linux-specific flags. By default controllers' and Linux' mapping
31 * Linux-specific in their .xlate callback. Though, 1:1 mapping is recommended.
44 * of_gpio_named_count() - Count GPIOs for a device
46 * @propname: property name containing gpio specifier(s)
53 * * %-EINVAL for an incorrectly formed "gpios" property, or
54 * * %-ENOENT for a missing "gpios" property.
69 return of_count_phandle_with_args(np, propname, "#gpio-cells"); in of_gpio_named_count()
[all …]
/linux/drivers/mfd/
H A Dmadera-core.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015-2018 Cirrus Logic
50 .name = "madera-ldo1",
62 { .name = "madera-pinctrl", },
63 { .name = "madera-irq", },
64 { .name = "madera-gpio", },
66 .name = "madera-extcon",
71 .name = "cs47l15-codec",
86 { .name = "madera-pinctrl", },
87 { .name = "madera-irq", },
[all …]
H A Dsun6i-prcm.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
7 * Allwinner PRCM (Power/Reset/Clock Management) driver
48 .name = "sun6i-a31-ar100-clk",
49 .of_compatible = "allwinner,sun6i-a31-ar100-clk",
54 .name = "sun6i-a31-apb0-clk",
55 .of_compatible = "allwinner,sun6i-a31-apb0-clk",
60 .name = "sun6i-a31-apb0-gates-clk",
61 .of_compatible = "allwinner,sun6i-a31-apb0-gates-clk",
66 .name = "sun6i-a31-ir-clk",
[all …]
/linux/drivers/clk/
H A Dclk-aspeed.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <linux/clk-provider.h>
10 #include <linux/reset-controller.h>
17 * struct aspeed_gate_data - Aspeed gated clocks
19 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
20 * reset is required when enabling the clock
21 * @name: the clock name
22 * @parent_name: the name of the parent clock
28 const char *name; member
34 * struct aspeed_clk_gate - Aspeed specific clk_gate structure
[all …]
/linux/drivers/media/pci/cx23885/
H A Dcx23885-cards.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <media/drv-intf/cx25840.h>
19 #include "netup-eeprom.h"
20 #include "netup-init.h"
21 #include "altera-ci.h"
24 #include "cx23888-ir.h"
29 "NetUP Dual DVB-T/C CI card revision");
35 "\t\t\tHVR-1250 (reported safe)\n"
41 /* ------------------------------------------------------------------ */
46 .name = "UNKNOWN/GENERIC",
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-g12a-power.h>
10 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
11 #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
14 tdmif_a: audio-controller-0 {
15 compatible = "amlogic,axg-tdm-iface";
16 #sound-dai-cells = <0>;
17 sound-name-prefix = "TDM_A";
[all …]
H A Dmeson-sm1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-sm1-power.h>
10 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
11 #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
16 tdmif_a: audio-controller-0 {
17 compatible = "amlogic,axg-tdm-iface";
18 #sound-dai-cells = <0>;
19 sound-name-prefix = "TDM_A";
[all …]
/linux/include/linux/
H A Dreset-controller.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct reset_control_ops - reset controller driver callbacks
12 * @reset: for self-deasserting resets, does all necessary
13 * things to reset the device
14 * @assert: manually assert the reset line, if supported
15 * @deassert: manually deassert the reset line, if supported
16 * @status: return the status of the reset line, if supported
19 int (*reset)(struct reset_controller_dev *rcdev, unsigned long id); member
30 * struct reset_control_lookup - represents a single lookup entry
32 * @list: internal list of all reset lookup entries
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Drohm,bd71847-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd71847-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
14 single-core, dual-core, and quad-core SoCs such as NXP-i.MX 8M. It is
18 …/www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-applica…
19 …//www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-applic…
24 - rohm,bd71847
25 - rohm,bd71850
[all …]
/linux/arch/arm/mach-omap2/
H A Domap_hwmod.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2011 Nokia Corporation
6 * Copyright (C) 2011-2012 Texas Instruments, Inc.
15 * ------------
21 * TI's documentation, on-chip devices are referred to as "OMAP
26 * Most of the address and data flow between modules is via OCP-based
29 * and reset signaling, supply power, and connect the modules to
32 * OMAP hwmod provides a consistent way to describe the on-chip
36 * to reset, enable, idle, and disable these hardware blocks. And
42 * -----------
[all …]
/linux/drivers/clk/qcom/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
10 #include <linux/clk-provider.h>
11 #include <linux/interconnect-clk.h>
12 #include <linux/reset-controller.h>
16 #include "clk-rcg.h"
17 #include "clk-regmap.h"
18 #include "reset.h"
22 struct qcom_reset_controller reset; member
33 if (!f->freq) in qcom_find_freq()
[all …]
/linux/drivers/soc/dove/
H A Dpmu.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/reset.h>
14 #include <linux/reset-controller.h>
37 struct reset_controller_dev reset; member
42 * The PMU contains a register to reset various subsystems within the
43 * SoC. Export this as a reset controller.
46 #define rcdev_to_pmu(rcdev) container_of(rcdev, struct pmu_data, reset)
54 spin_lock_irqsave(&pmu->lock, flags); in pmu_reset_reset()
55 val = readl_relaxed(pmu->pmc_base + PMC_SW_RST); in pmu_reset_reset()
56 writel_relaxed(val & ~BIT(id), pmu->pmc_base + PMC_SW_RST); in pmu_reset_reset()
[all …]
/linux/drivers/pmdomain/bcm/
H A Dbcm2835-power.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/soc/bcm2835-pm.h>
12 #include <linux/mfd/bcm2835-pm.h>
16 #include <linux/reset-controller.h>
109 #define PM_READ(reg) readl(power->base + (reg))
110 #define PM_WRITE(reg, val) writel(PM_PASSWORD | (val), power->base + (reg))
149 struct reset_controller_dev reset; member
154 void __iomem *base = power->asb; in bcm2835_asb_control()
163 if (power->rpivid_asb) in bcm2835_asb_control()
164 base = power->rpivid_asb; in bcm2835_asb_control()
[all …]
/linux/drivers/leds/
H A Dleds-bd2802.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * leds-bd2802.c - RGB LED Driver
8 * Datasheet: http://www.rohm.com/products/databook/driver/pdf/bd2802gu-e.pdf
16 #include <linux/leds-bd2802.h>
70 struct gpio_desc *reset; member
90 * therefore BD2802GU doesn't enter reset state.
104 /*--------------------------------------------------------------*/
106 /*--------------------------------------------------------------*/
113 return !led->led[id].r; in bd2802_is_rgb_off()
115 return !led->led[id].g; in bd2802_is_rgb_off()
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dsnps,dwc-qos-ethernet.txt7 IP block. The IP supports multiple options for bus type, clocking and reset
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
[all …]
/linux/drivers/gpu/drm/i915/gt/
H A Dselftest_reset.c1 // SPDX-License-Identifier: MIT
22 struct i915_ggtt *ggtt = gt->ggtt; in __igt_reset_stolen()
23 const struct resource *dsm = &gt->i915->dsm.stolen; in __igt_reset_stolen()
34 if (!drm_mm_node_allocated(&ggtt->error_capture)) in __igt_reset_stolen()
43 return -ENOMEM; in __igt_reset_stolen()
47 err = -ENOMEM; in __igt_reset_stolen()
52 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in __igt_reset_stolen()
62 if (!(mask & engine->mask)) in __igt_reset_stolen()
83 dma_addr_t dma = (dma_addr_t)dsm->start + (page << PAGE_SHIFT); in __igt_reset_stolen()
87 ggtt->vm.insert_page(&ggtt->vm, dma, in __igt_reset_stolen()
[all …]
/linux/drivers/reset/starfive/
H A Dreset-starfive-jh7110.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Reset driver for the StarFive JH7110 SoC
10 #include <soc/starfive/reset-starfive-jh71x0.h>
12 #include "reset-starfive-jh71x0.h"
14 #include <dt-bindings/reset/starfive,jh7110-crg.h>
55 struct jh7110_reset_info *info = (struct jh7110_reset_info *)(id->driver_data); in jh7110_reset_probe()
57 void __iomem *base = rdev->base; in jh7110_reset_probe()
60 return -ENODEV; in jh7110_reset_probe()
62 return reset_starfive_jh71x0_register(&adev->dev, adev->dev.parent->of_node, in jh7110_reset_probe()
63 base + info->assert_offset, in jh7110_reset_probe()
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-clearfog-gtr.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
9 SERDES mapping -
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
12 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
14 4. mini PCIe CON2 - PCIe2
17 USB 2.0 mapping -
18 0. USB 2.0 - 0 USB pins header CON12
19 1. USB 2.0 - 1 mini PCIe CON2
20 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
[all …]
/linux/drivers/accessibility/speakup/
H A Dkobjects.c1 // SPDX-License-Identifier: GPL-2.0
7 * This code is based on kobject-example.c, which came with linux 2.6.x.
9 * Copyright (C) 2004-2007 Greg Kroah-Hartman <greg@kroah.com>
44 if (strcmp("characters", attr->attr.name) == 0) { in chars_chartab_show()
71 bufsize -= len; in chars_chartab_show()
75 return buf_pointer - buf; in chars_chartab_show()
82 static void report_char_chartab_status(int reset, int received, int used, in report_char_chartab_status() argument
92 if (reset) { in report_char_chartab_status()
93 pr_info("%s reset to defaults\n", object_type[do_characters]); in report_char_chartab_status()
99 snprintf(buf + (len - 1), sizeof(buf) - (len - 1), in report_char_chartab_status()
[all …]
/linux/tools/virtio/
H A Dvirtio_test.c1 // SPDX-License-Identifier: GPL-2.0
22 #define RANDOM_BATCH -1
49 static const struct vhost_vring_file no_backend = { .fd = -1 },
55 struct vq_info *info = vq->priv; in vq_notify()
58 r = write(info->kick, &v, sizeof v); in vq_notify()
70 struct vhost_vring_state state = { .index = info->idx }; in vhost_vq_setup()
71 struct vhost_vring_file file = { .index = info->idx }; in vhost_vq_setup()
72 unsigned long long features = dev->vdev.features; in vhost_vq_setup()
74 .index = info->idx, in vhost_vq_setup()
75 .desc_user_addr = (uint64_t)(unsigned long)info->vring.desc, in vhost_vq_setup()
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
17 - reg : shall be the physical PLL register address for the pll clock.
[all …]

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