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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmti,gic.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
23 "#interrupt-cells":
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/linux/Documentation/devicetree/bindings/powerpc/
H A Dibm,powerpc-cpu-features.txt3 (skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)
9 ibm,powerpc-cpu-features binding
12 This device tree binding describes CPU features available to software, with
19 /cpus/ibm,powerpc-cpu-features node binding
20 -------------------------------------------
22 Node: ibm,powerpc-cpu-features
24 Description: Container of CPU feature nodes.
26 The node name must be "ibm,powerpc-cpu-features".
35 - compatible
38 Definition: "ibm,powerpc-cpu-features"
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/linux/arch/xtensa/include/asm/
H A Dmmu_context.h8 * Copyright (C) 2001 - 2013 Tensilica Inc.
23 #include <asm/vectors.h>
27 #include <asm-generic/mm_hooks.h>
28 #include <asm-generic/percpu.h>
35 #define cpu_asid_cache(cpu) per_cpu(asid_cache, cpu) argument
39 * any user or kernel context. We use the reserved values in the
44 * 2 reserved
45 * 3 reserved
51 #define ASID_MASK ((1 << XCHAL_MMU_ASID_BITS) - 1)
70 static inline void get_new_mmu_context(struct mm_struct *mm, unsigned int cpu) in get_new_mmu_context() argument
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/linux/kernel/irq/
H A Dmatrix.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/cpu.h>
41 * irq_alloc_matrix - Allocate a irq_matrix structure and initialize it
51 unsigned int cpu, matrix_size = BITS_TO_LONGS(matrix_bits); in irq_alloc_matrix() local
58 m->system_map = &m->scratch_map[matrix_size]; in irq_alloc_matrix()
60 m->matrix_bits = matrix_bits; in irq_alloc_matrix()
61 m->alloc_start = alloc_start; in irq_alloc_matrix()
62 m->alloc_end = alloc_end; in irq_alloc_matrix()
63 m->alloc_size = alloc_end - alloc_start; in irq_alloc_matrix()
64 m->maps = __alloc_percpu(struct_size(m->maps, alloc_map, matrix_size * 2), in irq_alloc_matrix()
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/linux/drivers/irqchip/
H A Dirq-mips-gic.c6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
10 #define pr_fmt(fmt) "irq-mips-gic: " fmt
26 #include <asm/mips-cps.h>
30 #include <dt-bindings/interrupt-controller/mips-gic.h>
35 /* Add 2 to convert GIC CPU pin to core interrupt */
44 #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
47 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
71 unsigned int cpu; in __gic_with_next_online_cpu() local
73 /* Discover the next online CPU */ in __gic_with_next_online_cpu()
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/linux/arch/x86/kernel/apic/
H A Dvector.c1 // SPDX-License-Identifier: GPL-2.0-only
30 unsigned int cpu; member
78 info->mask = mask; in init_irq_alloc_info()
94 while (irqd->parent_data) in apic_chip_data()
95 irqd = irqd->parent_data; in apic_chip_data()
97 return irqd->chip_data; in apic_chip_data()
104 return apicd ? &apicd->hw_irq_cfg : NULL; in irqd_cfg()
119 INIT_HLIST_NODE(&apicd->clist); in alloc_apic_chip_data()
129 unsigned int cpu) in apic_update_irq_cfg() argument
135 apicd->hw_irq_cfg.vector = vector; in apic_update_irq_cfg()
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H A Dapic.c1 // SPDX-License-Identifier: GPL-2.0-only
13 * Mikael Pettersson : Power Management for UP-APIC.
35 #include <linux/cpu.h>
44 #include <asm/pc-conf-reg.h>
66 #include <asm/intel-family.h>
68 #include <asm/cpu.h>
125 * +1=force-enable
201 /* AMD systems use old APIC versions, so check the CPU */ in modern_apic()
215 * so apic->write/read doesn't do anything
243 * lapic_get_maxlvt - get the maximum number of local vector table entries
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/linux/arch/arc/kernel/
H A Dentry-arcv2.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling
17 ; first 16 lines are reserved for exceptions and are not configurable.
20 .cpu HS
29 # Initial 16 slots are Exception Vectors
44 VECTOR reserved ; Reserved slots
45 VECTOR reserved ; Reserved slots
47 # Begin Interrupt Vectors
58 .rept NR_CPU_IRQS - 8
64 reserved: label
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H A Dentry-compact.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low Level Interrupts/Traps/Exceptions(non-TLB) Handling for ARCompact ISA
5 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
6 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
9 * -Userspace unaligned access emulation
12 * -traced syscall return code (r0) was not saved into pt_regs for restoring
13 * into user reg-file when traded task rets to user space.
14 * -syscalls needing arch-wrappers (mainly for passing sp as pt_regs)
15 * were not invoking post-syscall trace hook (jumping directly into
19 * -Vector table jumps (@8 bytes) converted into branches (@4 bytes)
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/linux/arch/arm64/kernel/
H A Dproton-pack.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability
12 * Copyright (C) 2018 ARM Ltd, All Rights Reserved.
20 #include <linux/arm-smccc.h>
22 #include <linux/cpu.h>
28 #include <asm/debug-monitors.h>
32 #include <asm/vectors.h>
37 * onlining a late CPU.
70 * This one sucks. A CPU is either:
72 * - Mitigated in hardware and advertised by ID_AA64PFR0_EL1.CSV2.
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H A Dentry.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
10 #include <linux/arm-smccc.h>
16 #include <asm/asm-offsets.h>
30 #include <asm/asm-uaccess.h>
45 * skipped by the trampoline vectors, to trigger the cleanup.
64 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
66 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
67 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
89 * after panic() re-enables interrupts.
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/linux/Documentation/arch/arm/
H A Dmemory.rst13 The ARM CPU is capable of addressing a maximum of 4GB virtual memory
30 ffff1000 ffff7fff Reserved.
33 ffff0000 ffff0fff CPU vector page.
34 The CPU vectors are mapped here if the
35 CPU supports vector relocation (control
39 in proc-xscale.S to flush the whole data
43 DTCM mounted inside the CPU.
46 ITCM mounted inside the CPU.
53 ff800000 ffbfffff Permanent, fixed read-only mapping of the
59 VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space.
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/linux/arch/x86/include/asm/
H A Dsegment.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 ((((base) & _AC(0xff000000,ULL)) << (56-24)) | \
16 (((limit) & _AC(0x000f0000,ULL)) << (48-16)) | \
61 * The layout of the per-CPU GDT under Linux:
63 * 0 - null <=== cacheline #1
64 * 1 - reserved
65 * 2 - reserved
66 * 3 - reserved
68 * 4 - unused <=== cacheline #2
69 * 5 - unused
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/linux/arch/powerpc/kernel/
H A Dhead_book3s_32.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * Low-level exception handlers and MMU support
14 * This file contains the low-level support and setup for the
30 #include <asm/asm-offsets.h>
34 #include <asm/feature-fixups.h>
40 /* see the comment for clear_bats() -- Cort */ \
65 * -- Cort
77 * pointer (r1) points to just below the end of the half-meg region
78 * from 0x380000 - 0x400000, which is mapped in already.
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H A Dhead_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * Low-level exception handlers and MMU support
16 * This file contains the entry point for the 64-bit kernel along
17 * with some early initialization code common to all 64-bit powerpc
28 #include <asm/head-64.h>
29 #include <asm/asm-offsets.h>
42 #include <asm/ppc-opcode.h>
43 #include <asm/feature-fixups.h>
45 #include <asm/exception-64s.h>
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/linux/fs/xfs/
H A Dxfs_log_priv.h1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2000-2003,2005 Silicon Graphics, Inc.
4 * All Rights Reserved.
74 * By covering, we mean changing the h_tail_lsn in the last on-disk
75 * log write such that no allocation transactions will be re-done during
76 * recovery after a system crash. Recovery starts at the last on-disk
80 * space allocation transactions which can undo non-transactional changes
93 * non-dummy transaction. The first dummy changes the h_tail_lsn to
102 * IDLE -- no logging has been done on the file system or
104 * NEED -- logging has occurred and we need a dummy transaction
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H A Dxfs_log_cil.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2010 Red Hat, Inc. All Rights Reserved.
27 * We don't reserve any space for the ticket - we are going to steal whatever
45 tic->t_curr_res = 0; in xlog_cil_ticket_alloc()
46 tic->t_iclog_hdrs = 0; in xlog_cil_ticket_alloc()
53 struct xlog *log = cil->xc_log; in xlog_cil_set_iclog_hdr_count()
55 atomic_set(&cil->xc_iclog_hdrs, in xlog_cil_set_iclog_hdr_count()
57 (log->l_iclog_size - log->l_iclog_hsize))); in xlog_cil_set_iclog_hdr_count()
65 * Note: for this to be used in a non-racy manner, it has to be called with
74 if (test_bit(XLOG_CIL_EMPTY, &cil->xc_flags)) in xlog_item_in_current_chkpt()
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/linux/arch/powerpc/include/asm/
H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * number used in the Programming Environments Manual For 32-Bit
17 #include <asm/asm-const.h>
18 #include <asm/feature-fixups.h>
74 /* so tests for these bits fail on 32-bit */
116 #define MSR_TS_N 0 /* Non-transactional */
120 #define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) == MSR_TS_MASK) /* Reserved */
161 /* Power Management - Processor Stop Status and Control Register Fields */
165 #define PSSCR_PSLL_MASK 0x000F0000 /* Power-Saving Level Limit */
169 #define PSSCR_PLS 0xf000000000000000 /* Power-saving Level Status */
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/linux/arch/powerpc/sysdev/
H A Dmpic.c9 * Copyright 2010-2012 Freescale Semiconductor, Inc.
153 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
163 unsigned int cpu = 0; in mpic_processor_id() local
165 if (!(mpic->flags & MPIC_SECONDARY)) in mpic_processor_id()
166 cpu = hard_smp_processor_id(); in mpic_processor_id()
168 return cpu; in mpic_processor_id()
183 return dcr_read(rb->dhost, reg); in _mpic_read()
186 return in_be32(rb->base + (reg >> 2)); in _mpic_read()
189 return in_le32(rb->base + (reg >> 2)); in _mpic_read()
200 dcr_write(rb->dhost, reg, value); in _mpic_write()
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/linux/arch/arm/mach-sa1100/
H A Dgeneric.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-sa1100/generic.c
15 #include <linux/dma-mapping.h>
23 #include <linux/irqchip/irq-sa11x0.h>
67 unsigned int sa11x0_getspeed(unsigned int cpu) in sa11x0_getspeed() argument
69 if (cpu) in sa11x0_getspeed()
75 * Default power-off for SA1100
83 /* enable wake-up on GPIO0 (Assabet...) */ in sa1100_power_off()
102 /* Use on-chip reset capability */ in sa11x0_restart()
110 dev->dev.platform_data = data; in sa11x0_register_device()
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/linux/drivers/virt/nitro_enclaves/
H A Dne_pci_dev.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2020-2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
21 * PCI_DEVICE_ID_NE - Nitro Enclaves PCI device id.
25 * PCI_BAR_NE - Nitro Enclaves PCI device MMIO BAR.
34 * NE_ENABLE - (1 byte) Register to notify the device that the driver is using
42 * NE_VERSION - (2 bytes) Register to select the device run-time version
49 * NE_COMMAND - (4 bytes) Register to notify the device what command was
50 * requested (Write-Only).
55 * NE_EVTCNT - (4 bytes) Register to notify the driver that a reply or a device
56 * event is available (Read-Only):
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/linux/Documentation/admin-guide/hw-vuln/
H A Drsb.rst1 .. SPDX-License-Identifier: GPL-2.0
4 RSB-related mitigations
8 Please keep this document up-to-date, otherwise you will be
17 amongst a myriad of microarchitecture-specific documents.
20 once place and clarify the reasoning behind the current RSB-related
22 the current kernel mitigations: what are the RSB-related attack vectors
39 ----
47 RSB poisoning is a technique used by SpectreRSB [#spectre-rsb]_ where
49 to speculate to an attacker-controlled address. This can happen when
52 * All attack vectors can potentially be mitigated by flushing out any
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/linux/arch/arm64/kvm/
H A Darm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
85 int r = -EINVAL; in kvm_vm_ioctl_enable_cap()
87 if (cap->flags) in kvm_vm_ioctl_enable_cap()
88 return -EINVAL; in kvm_vm_ioctl_enable_cap()
90 if (kvm_vm_is_protected(kvm) && !kvm_pvm_ext_allowed(cap->cap)) in kvm_vm_ioctl_enable_cap()
91 return -EINVAL; in kvm_vm_ioctl_enable_cap()
93 switch (cap->cap) { in kvm_vm_ioctl_enable_cap()
97 &kvm->arch.flags); in kvm_vm_ioctl_enable_cap()
100 mutex_lock(&kvm->lock); in kvm_vm_ioctl_enable_cap()
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/linux/drivers/net/ethernet/brocade/bna/
H A Dbnad.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Linux network driver for QLogic BR-series Converged Network Adapter.
6 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
7 * Copyright (c) 2014-2015 QLogic Corporation
8 * All rights reserved
58 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
59 ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \
60 ((_bnad)->pcidev->irq))
64 (_res_info)->res_type = BNA_RES_T_MEM; \
65 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
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/linux/arch/arm/mm/
H A Dmmu.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1995-2005 Russell King
46 * zero-initialized data and COW.
52 * The pmd table for the upper-most set of pages.
143 int i, selected = -1; in early_cachepolicy()
154 if (selected == -1) in early_cachepolicy()
240 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
440 * Adjust the PMD section entries according to the CPU in use.
467 pr_warn("Forcing write-allocate cache policy for SMP\n"); in build_mem_type_table()
478 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those in build_mem_type_table()
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