| /linux/Documentation/devicetree/bindings/dma/ |
| H A D | ingenic,dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: dma-controller.yaml#
18 - enum:
19 - ingenic,jz4740-dma
20 - ingenic,jz4725b-dma
21 - ingenic,jz4755-dma
22 - ingenic,jz4760-dma
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| H A D | ti-edma.txt | 8 ------------------------------------------------------------------------------
12 --------------------
13 - compatible: Should be:
14 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
16 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
18 - #dma-cells: Should be set to <2>. The first number is the DMA request
20 - reg: Memory map of eDMA CC
21 - reg-names: "edma3_cc"
22 - interrupts: Interrupt lines for CCINT, MPERR and CCERRINT.
23 - interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint"
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| H A D | brcm,bcm2835-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/brcm,bcm2835-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Saenz Julienne <nsaenz@kernel.org>
13 The BCM2835 DMA controller has 16 channels in total. Only the lower
14 13 channels have an associated IRQ. Some arbitrary channels are used by the
15 VideoCore firmware (1,3,6,7 in the current firmware version). The channels
19 - $ref: dma-controller.yaml#
23 const: brcm,bcm2835-dma
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| H A D | ti-dma-crossbar.txt | 4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
5 "ti,am335x-edma-crossbar" for AM335x and AM437x
6 - reg: Memory map for accessing module
7 - #dma-cells: Should be set to match with the DMA controller's dma-cells
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
13 - dma-requests: Number of DMA requests the controller can handle
16 - ti,dma-safe-map: Safe routing value for unused request lines
17 - ti,reserved-dma-request-ranges: DMA request ranges which should not be used
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| /linux/drivers/net/wireless/intel/iwlwifi/fw/api/ |
| H A D | rfi.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2020-2021, 2023 Intel Corporation
13 * struct iwl_rfi_lut_entry - an entry in the RFI frequency LUT.
16 * @channels: channels that can be interfered at frequency freq (at most 15)
21 u8 channels[IWL_RFI_LUT_ENTRY_CHANNELS_NUM]; member
26 * struct iwl_rfi_config_cmd - RFI configuration table
30 * @reserved: (reserved/padding)
35 u8 reserved[3]; member
39 * enum iwl_rfi_freq_table_status - status of the frequency table query
51 * struct iwl_rfi_freq_table_resp_cmd - get the rfi freq table used by FW
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| /linux/drivers/comedi/drivers/ |
| H A D | amplc_dio200.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
9 * COMEDI - Linux Control and Measurement Device Interface
24 * [0] - I/O port base address
25 * [1] - IRQ (optional, but commands won't work without it)
32 * ------------- ------------- -------------
34 * 0 PPI-X PPI-X PPI-X
35 * 1 CTR-Y1 PPI-Y PPI-Y
36 * 2 CTR-Y2 CTR-Z1* CTR-Z1
37 * 3 CTR-Z1 INTERRUPT* CTR-Z2
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| H A D | amplc_dio200_pci.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
8 * COMEDI - Linux Control and Measurement Device Interface
30 * ------------- ------------- -------------
32 * 0 PPI-X PPI-X PPI-X
33 * 1 PPI-Y UNUSED UNUSED
34 * 2 CTR-Z1 PPI-Y UNUSED
35 * 3 CTR-Z2 UNUSED UNUSED
36 * 4 INTERRUPT CTR-Z1 CTR-Z1
37 * 5 CTR-Z2 CTR-Z2
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| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | vidioc-g-modulator.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_G_MODULATOR - VIDIOC_S_MODULATOR - Get or set modulator attributes
39 ``index`` field and zero out the ``reserved`` array of a struct
49 initialize the ``index`` and ``txsubchans`` fields and the ``reserved``
52 this is a write-only ioctl, it does not return the actual audio
67 .. flat-table:: struct v4l2_modulator
68 :header-rows: 0
69 :stub-columns: 0
72 * - __u32
73 - ``index``
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| /linux/sound/soc/sof/ |
| H A D | ipc4-topology.h | 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
15 #define SOF_IPC4_FW_PAGE(x) ((((x) + BIT(12) - 1) & ~(BIT(12) - 1)) >> 12)
16 #define SOF_IPC4_FW_ROUNDUP(x) (((x) + BIT(6) - 1) & (~(BIT(6) - 1)))
22 * LL domain - Low latency domain
23 * DP domain - Data processing domain
80 * The base of multi-gateways. Multi-gateways addressing starts from
81 * ALH_MULTI_GTW_BASE and there are ALH_MULTI_GTW_COUNT multi-sources
82 * and ALH_MULTI_GTW_COUNT multi-sinks available.
84 * ALH_MULTI_GTW_BASE + ALH_MULTI_GTW_COUNT - 1.
108 * HD-A gateways.
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| /linux/include/xen/interface/io/ |
| H A D | sndif.h | 1 /* SPDX-License-Identifier: MIT */
5 * Unified sound-device I/O interface for Xen guest OSes.
7 * Copyright (C) 2013-2015 GlobalLogic Inc.
8 * Copyright (C) 2016-2017 EPAM Systems Inc.
34 * Front->back notifications: when enqueuing a new request, sending a
36 * hold-off mechanism provided by the ring macros). Backends must set
39 * Back->front notifications: when enqueuing a new response, sending a
41 * hold-off mechanism provided by the ring macros). Frontends must set
44 * The two halves of a para-virtual sound card driver utilize nodes within
58 * Note: depending on the use-case backend can expose more sound cards and
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| /linux/Documentation/driver-api/rapidio/ |
| H A D | tsi721.rst | 2 RapidIO subsystem mport driver for IDT Tsi721 PCI Express-to-SRIO bridge.
10 doorbells, inbound maintenance port-writes and RapidIO messaging.
13 channels. This mechanism provides access to larger range of hop counts and
16 RapidIO messaging support uses dedicated messaging channels for each mailbox.
23 - 'dbg_level'
24 - This parameter allows to control amount of debug information
32 - 'dma_desc_per_channel'
33 - This parameter defines number of hardware buffer
37 - 'dma_txqueue_sz'
38 - DMA transactions queue size. Defines number of pending
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| /linux/drivers/edac/ |
| H A D | i3000_edac.c | 25 /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
33 * 7:1 reserved
39 * 6:1 reserved
54 deap |= (edeap & 1) << (32 - PAGE_SHIFT); in deap_pfn()
60 return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK; in deap_offset()
75 * 15:12 reserved
78 * 10 reserved
79 * 9 LOCK to non-DRAM Memory Flag (LCKF)
81 * 7:2 reserved
82 * 1 Multi-bit DRAM ECC Error Flag (DMERR)
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| H A D | i82975x_edac.c | 34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
37 * 31:7 128 byte cache-line address
38 * 6:1 reserved
49 * 1h:7h reserved
50 * More - See Page 65 of Intel DocSheet.
55 * 15:12 reserved
57 * 10 reserved
58 * 9 non-DRAM lock error (ndlock)
60 * 7:2 reserved
73 * 15:12 reserved
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| /linux/drivers/interconnect/qcom/ |
| H A D | icc-rpmh.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
10 #include <dt-bindings/interconnect/qcom,icc.h>
17 * struct qcom_icc_provider - Qualcomm specific interconnect provider
43 * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager (BCM)
47 * @reserved: reserved field
53 u8 reserved; member
59 * struct qcom_icc_qosbox - Qualcomm specific QoS config
82 * struct qcom_icc_node - Qualcomm specific interconnect nodes
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| /linux/sound/soc/amd/ |
| H A D | acp.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
73 /* Playback DMA channels */
77 /* Capture DMA channels */
81 /* Playback DMA Channels for I2S BT instance */
85 /* Capture DMA Channels for I2S BT Instance */
89 /* Playback DMA channels for I2S MICSP instance */
217 /* Reserved for future use */
218 u32 reserved; member
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| /linux/Documentation/trace/coresight/ |
| H A D | panic.rst | 6 ------------
11 -----------------------------------
15 a. Support for allocation of trace buffer pages from reserved memory area.
25 Allocation of trace buffer pages from reserved RAM
27 A new optional device tree property "memory-region" is added to the
37 For ETR sink devices, this reserved region will be used for both trace
40 and they would be synced to reserved region for retrieval.
53 Comparator --->External out --->CTI -->External In---->ETR/ETF stop
61 A new optional device property "memory-region" is added to
73 ETR sinks should have trace buffers allocated from reserved memory,
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| /linux/include/sound/sof/ |
| H A D | dai-intel.h | 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
58 /* DMIC max. four controllers for eight microphone channels */
61 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
93 /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */
98 uint32_t channels; member
101 /* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */
106 uint32_t channels; member
108 /* reserved for future use */
109 uint32_t reserved[13]; member
112 /* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */
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| H A D | channel_map.h | 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
16 * \brief Channel map, specifies transformation of one-to-many or many-to-one.
18 * In case of one-to-many specifies how the output channels are computed out of
20 * in case of many-to-one specifies how a single target channel is computed
29 * Channel mask describes which channels are taken into account on the "many"
30 * side. Bit[i] set to 1 means that i-th channel is used for computation
41 uint32_t reserved; member
57 uint32_t reserved[3]; member
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| /linux/Documentation/hwmon/ |
| H A D | twl4030-madc-hwmon.rst | 1 Kernel driver twl4030-madc
8 Prefix: 'twl4030-madc'
12 J Keerthy <j-keerthy@ti.com>
15 -----------
18 other things it contains a 10-bit A/D converter MADC. The converter has 16
19 channels which can be used in different modes.
22 See this table for the meaning of the different channels
40 13 Reserved
41 14 Reserved
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| /linux/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/ |
| H A D | pool.c | 1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2019-2020, Mellanox Technologies inc. All rights reserved. */
25 if (!xsk->pools) { in mlx5e_xsk_get_pools()
26 xsk->pools = kcalloc(MLX5E_MAX_NUM_CHANNELS, in mlx5e_xsk_get_pools()
27 sizeof(*xsk->pools), GFP_KERNEL); in mlx5e_xsk_get_pools()
28 if (unlikely(!xsk->pools)) in mlx5e_xsk_get_pools()
29 return -ENOMEM; in mlx5e_xsk_get_pools()
32 xsk->refcnt++; in mlx5e_xsk_get_pools()
33 xsk->ever_used = true; in mlx5e_xsk_get_pools()
40 if (!--xsk->refcnt) { in mlx5e_xsk_put_pools()
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| /linux/drivers/net/wireless/ti/wl18xx/ |
| H A D | scan.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2012 Texas Instruments. All rights reserved.
58 u8 passive[SCAN_MAX_BANDS]; /* number of passive scan channels */
59 u8 active[SCAN_MAX_BANDS]; /* number of active scan channels */
60 u8 dfs; /* number of dfs channels in 5ghz */
61 u8 passive_active; /* number of passive before active channels 2.4ghz */
66 u8 total_cycles; /* 0 - infinite */
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| /linux/drivers/dma/ |
| H A D | tegra210-adma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
18 #include "virt-dma.h"
84 * struct tegra_adma_chip_data - Tegra chip specific data
100 * @ch_req_max: Maximum number of Tx or Rx channels available.
102 * @nr_channels: Number of DMA channels available.
134 * struct tegra_adma_chan_regs - Tegra ADMA channel registers
148 * struct tegra_adma_desc - Tegra ADMA descriptor to manage transfer requests.
159 * struct tegra_adma_chan - Tegra ADMA channel information
184 * struct tegra_adma - Tegra ADMA controller information
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| /linux/arch/powerpc/include/asm/ |
| H A D | 8xx_immap.h | 10 * functional files.....but anyone else is welcome to try. -- Dan
95 /*-----------------------------------------------------------------------
96 * BR - Memory Controller: Base Register 16-9
112 /*-----------------------------------------------------------------------
113 * OR - Memory Controller: Option Register 16-11
197 char res[0x74]; /* Reserved area */
227 /* The key to unlock registers maintained by keep-alive power.
363 typedef struct scc { /* Serial communication channels */
378 typedef struct smc { /* Serial management channels */
395 ushort res1; /* reserved */
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| /linux/drivers/net/wireless/intel/iwlegacy/ |
| H A D | 4965.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
79 * Acquire il->lock before calling this function !
83 * il4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
84 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
87 * NOTE: Acquire il->lock before calling this function !
181 * The first queue used for block-ack aggregation is #7 (4965 only).
182 * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
194 #define IL49_RTC_INST_SIZE (IL49_RTC_INST_UPPER_BOUND - \
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| /linux/include/linux/ |
| H A D | hyperv.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
48 * gva: |-- 64k --|-- 64k --| ... |
59 * gva: |-- 64k --|-- 64k --| ... |-- 64k --|-- 64k --| ... |
69 * index: 0 1 2 ... 16 ... n-15 n-14 n-13 ... 2n-30
76 /* Single-page buffer */
83 /* Multiple-page buffer */
92 * Multiple-page buffer array; the pfn array is variable size:
123 * WS2012/Win8 and later versions of Hyper-V implement interrupt
125 * is set by the host on the host->guest ring buffer, and by the
126 * guest on the guest->host ring buffer.
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