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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra194-p3509-0000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
19 #address-cells = <1>;
20 #size-cells = <0>;
25 i2s3_cif_ep: endpoint {
26 remote-endpoint = <&xbar_i2s3_ep>;
33 i2s3_dap_ep: endpoint {
34 dai-format = "i2s";
[all …]
H A Dtegra194-p2972-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra194-p2888.dtsi"
11 compatible = "nvidia,p2972-0000", "nvidia,tegra194";
24 #address-cells = <1>;
25 #size-cells = <0>;
30 i2s1_cif_ep: endpoint {
31 remote-endpoint = <&xbar_i2s1_ep>;
[all …]
H A Dtegra186-p2771-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra186-p3310.dtsi"
11 compatible = "nvidia,p2771-0000", "nvidia,tegra186";
23 #address-cells = <1>;
24 #size-cells = <0>;
29 i2s1_cif_ep: endpoint {
30 remote-endpoint = <&xbar_i2s1_ep>;
[all …]
H A Dtegra210-p2371-2180.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra210-p2180.dtsi"
5 #include "tegra210-p2597.dtsi"
9 compatible = "nvidia,p2371-2180", "nvidia,tegra210";
14 hvddio-pex-supply = <&vdd_1v8>;
15 dvddio-pex-supply = <&vdd_pex_1v05>;
16 vddio-pex-ctl-supply = <&vdd_1v8>;
19 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
20 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
[all …]
H A Dtegra210-p3450-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/linux-event-codes.h>
6 #include <dt-bindings/mfd/max77620.h>
12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";
22 stdout-path = "serial0:115200n8";
25 reserved-memory {
26 #address-cells = <2>;
27 #size-cells = <2>;
[all …]
H A Dtegra186-p3509-0000+p3636-0001.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/mfd/max77620.h>
12 compatible = "nvidia,p3509-0000+p3636-0001", "nvidia,tegra186";
30 stdout-path = "serial0:115200n8";
41 phy-reset-gpios = <&gpio_aon TEGRA186_AON_GPIO(AA, 6) GPIO_ACTIVE_LOW>;
42 phy-handle = <&phy>;
43 phy-mode = "rgmii-id";
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3660-coresight.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2016-2018 HiSilicon Ltd.
15 compatible = "arm,coresight-etm4x", "arm,primecell";
18 clock-names = "apb_pclk";
20 arm,coresight-loses-context-with-cpu;
22 out-ports {
24 etm0_out: endpoint {
25 remote-endpoint =
33 compatible = "arm,coresight-etm4x", "arm,primecell";
36 clock-names = "apb_pclk";
[all …]
H A Dhi6220-coresight.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
17 clock-names = "apb_pclk";
19 out-ports {
21 soc_funnel_out: endpoint {
22 remote-endpoint =
28 in-ports {
30 soc_funnel_in: endpoint {
31 remote-endpoint =
39 compatible = "arm,coresight-tmc", "arm,primecell";
[all …]
/linux/arch/arm/boot/dts/hisilicon/
H A Dhip04.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 HiSilicon Ltd.
6 * Copyright (C) 2013-2014 Linaro Ltd.
12 /* memory bus is 64-bit */
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "hisilicon,hip04-bootwrapper";
22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 #address-cells = <1>;
27 #size-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
24 operating-points = <
32 fsl,soc-operating-points = <
33 /* ARM kHz SOC-PU uV */
[all …]
H A Dimx6dl.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6dl-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
23 operating-points = <
29 fsl,soc-operating-points = <
30 /* ARM kHz SOC-PU uV */
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dulcb-kf-audio-graph-card2-mix+split.dtsi1 // SPDX-License-Identifier: GPL-2.0
12 * (A) CPU0 (2ch) <----> (2ch) (X) ak4613 (MIX-0)
13 * (B) CPU1 (2ch) --/ (MIX-1)
14 * (C) CPU3 (2ch) ----> (8ch) (Y) PCM3168A-p (TDM-0 : 0,1ch)
15 * (D) CPU2 (2ch) --/ (TDM-1 : 2,3ch)
16 * (E) CPU4 (2ch) --/ (TDM-2 : 4,5ch)
17 * (F) CPU5 (2ch) --/ (TDM-3 : 6,7ch)
18 * (G) CPU6 (2ch) <---- (6ch) (Z) PCM3168A-c (TDM-a: 0,1ch)
19 * (H) CPU7 (2ch) <--/ (TDM-b: 2,3ch)
20 * (I) CPU8 (2ch) <--/ (TDM-c: 4,5ch)
[all …]
H A Dulcb-kf-audio-graph-card-mix+split.dtsi1 // SPDX-License-Identifier: GPL-2.0
12 * (A) CPU0 (2ch) <----> (2ch) (X) ak4613 (MIX-0)
13 * (B) CPU1 (2ch) --/ (MIX-1)
14 * (C) CPU2 (2ch) ----> (8ch) (Y) PCM3168A-p (TDM-0 : 0,1ch)
15 * (D) CPU3 (2ch) --/ (TDM-1 : 2,3ch)
16 * (E) CPU4 (2ch) --/ (TDM-2 : 4,5ch)
17 * (F) CPU5 (2ch) --/ (TDM-3 : 6,7ch)
18 * (G) CPU6 (2ch) <---- (6ch) (Z) PCM3168A-c (TDM-a: 0,1ch)
19 * (H) CPU7 (2ch) <--/ (TDM-b: 2,3ch)
20 * (I) CPU8 (2ch) <--/ (TDM-c: 4,5ch)
[all …]
H A Dr8a77970-eagle-function-expansion.dtso1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
17 cvbs-in-cn4 {
18 compatible = "composite-video-connector";
22 cvbs_con: endpoint {
23 remote-endpoint = <&adv7482_ain7>;
30 hdmi-in-cn2 {
31 compatible = "hdmi-connector";
[all …]
H A Dr8a774c0-ek874-mipi-2.1.dts1 // SPDX-License-Identifier: GPL-2.0
4 * connected with aistarvision-mipi-v2-adapter board
9 /dts-v1/;
10 #include "r8a774c0-ek874.dts"
13 #include "aistarvision-mipi-adapter-2.1.dtsi"
16 …model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875) with aistarvision-mipi-v2-ada…
17 compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0";
37 csi40_in: endpoint {
38 clock-lanes = <0>;
39 data-lanes = <1 2>;
[all …]
/linux/arch/arm64/boot/dts/sprd/
H A Dsc9836.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #address-cells = <2>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
22 enable-method = "psci";
27 compatible = "arm,cortex-a53";
29 enable-method = "psci";
34 compatible = "arm,cortex-a53";
36 enable-method = "psci";
[all …]
H A Dums512.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/sprd,ums512-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <2>;
18 #size-cells = <0>;
20 cpu-map {
51 compatible = "arm,cortex-a55";
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-orangepi-5-max.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/soc/rockchip,vop2.h>
8 #include "rk3588-orangepi-5-compact.dtsi"
12 compatible = "xunlong,orangepi-5-max", "rockchip,rk3588";
14 hdmi0-con {
15 compatible = "hdmi-connector";
19 hdmi0_con_in: endpoint {
[all …]
H A Drk3588-orangepi-5-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/soc/rockchip,vop2.h>
11 #include <dt-bindings/usb/pd.h>
12 #include "rk3588-orangepi-5.dtsi"
16 compatible = "xunlong,orangepi-5-plus", "rockchip,rk3588";
18 hdmi0-con {
19 compatible = "hdmi-connector";
[all …]
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dmaxim,max9286.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jacopo Mondi <jacopo+renesas@jmondi.org>
12 - Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
13 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 - Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
18 Serial Links (GMSL) and outputs them on a CSI-2 D-PHY port using up to 4 data
28 '#address-cells':
31 '#size-cells':
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun8i-r40-tcon-top.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
22 / [0] TCON-LCD0
25 \ / [1] TCON-LCD1 - LCD1/LVDS1
26 TCON-TOP
27 / \ [2] TCON-TV0 [0] - TVE0/RGB
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dqcs8550-aim300-aiot.dts1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
9 #include "qcs8550-aim300.dtsi"
16 compatible = "qcom,qcs8550-aim300-aiot", "qcom,qcs8550-aim300", "qcom,qcs8550",
24 stdout-path = "serial0:115200n8";
27 gpio-keys {
28 compatible = "gpio-keys";
30 pinctrl-0 = <&volume_up_n>;
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 #address-cells = <1>;
14 #size-cells = <1>;
18 frame-number = <1>;
30 #mbox-cells = <1>;
32 clock-names = "apb_pclk";
36 compatible = "arm,mmu-400", "arm,smmu-v1";
[all …]
/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,omap-dss.txt5 -------------------
25 -----------
36 -------
39 name for each display. If no aliases are defined, a semi-random number is used
43 -------
45 A shortened example of the DSS description for OMAP4, with non-relevant parts
49 compatible = "ti,omap4-dss";
54 clock-names = "fck";
55 #address-cells = <1>;
56 #size-cells = <1>;
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dtoshiba,tc358775.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinay Simha BN <simhavcs@gmail.com>
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
25 - toshiba,tc358765
26 - toshiba,tc358775
32 vdd-supply:
[all …]

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