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/linux/arch/parisc/include/asm/
H A Dasmregs.h11 rp: .reg %r2
12 arg3: .reg %r23
13 arg2: .reg %r24
14 arg1: .reg %r25
15 arg0: .reg %r26
16 dp: .reg %r27
17 ret0: .reg %r28
18 ret1: .reg %r29
19 sl: .reg %r29
20 sp: .reg %r30
[all …]
/linux/arch/mips/include/asm/
H A Dasm-eva.h19 #define kernel_ll(reg, addr) "ll " reg ", " addr "\n" argument
20 #define kernel_sc(reg, addr) "sc " reg ", " addr "\n" argument
21 #define kernel_lw(reg, addr) "lw " reg ", " addr "\n" argument
22 #define kernel_lwl(reg, addr) "lwl " reg ", " addr "\n" argument
23 #define kernel_lwr(reg, addr) "lwr " reg ", " addr "\n" argument
24 #define kernel_lh(reg, addr) "lh " reg ", " addr "\n" argument
25 #define kernel_lb(reg, addr) "lb " reg ", " addr "\n" argument
26 #define kernel_lbu(reg, addr) "lbu " reg ", " addr "\n" argument
27 #define kernel_sw(reg, addr) "sw " reg ", " addr "\n" argument
28 #define kernel_swl(reg, addr) "swl " reg ", " addr "\n" argument
[all …]
/linux/drivers/net/ethernet/mscc/
H A Dvsc7514_regs.c72 REG(ANA_ADVLEARN, 0x009000),
73 REG(ANA_VLANMASK, 0x009004),
74 REG(ANA_PORT_B_DOMAIN, 0x009008),
75 REG(ANA_ANAGEFIL, 0x00900c),
76 REG(ANA_ANEVENTS, 0x009010),
77 REG(ANA_STORMLIMIT_BURST, 0x009014),
78 REG(ANA_STORMLIMIT_CFG, 0x009018),
79 REG(ANA_ISOLATED_PORTS, 0x009028),
80 REG(ANA_COMMUNITY_PORTS, 0x00902c),
81 REG(ANA_AUTOAGE, 0x009030),
[all …]
/linux/tools/testing/selftests/powerpc/include/
H A Dvmx_asm.h9 #define PUSH_VMX(pos,reg) \ argument
10 li reg,pos; \
11 stvx v20,reg,%r1; \
12 addi reg,reg,16; \
13 stvx v21,reg,%r1; \
14 addi reg,reg,16; \
15 stvx v22,reg,%r1; \
16 addi reg,reg,16; \
17 stvx v23,reg,%r1; \
18 addi reg,reg,16; \
[all …]
/linux/drivers/media/platform/samsung/s5p-jpeg/
H A Djpeg-hw-s5p.c19 unsigned long reg; in s5p_jpeg_reset() local
22 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
24 while (reg != 0) { in s5p_jpeg_reset()
26 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
37 unsigned long reg, m; in s5p_jpeg_input_raw_mode() local
45 reg = readl(regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
46 reg &= ~S5P_MOD_SEL_MASK; in s5p_jpeg_input_raw_mode()
47 reg |= m; in s5p_jpeg_input_raw_mode()
48 writel(reg, regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
53 unsigned long reg, m; in s5p_jpeg_proc_mode() local
[all …]
/linux/drivers/media/cec/platform/s5p/
H A Dexynos_hdmi_cecctrl.c26 unsigned int reg; in s5p_cec_set_divider() local
30 if (regmap_read(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, &reg)) { in s5p_cec_set_divider()
35 reg = (reg & ~(0x3FF << 16)) | (div_ratio << 16); in s5p_cec_set_divider()
37 if (regmap_write(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, reg)) { in s5p_cec_set_divider()
44 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_3); in s5p_cec_set_divider()
45 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_2); in s5p_cec_set_divider()
46 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_1); in s5p_cec_set_divider()
47 writeb(div_val, cec->reg + S5P_CEC_DIVISOR_0); in s5p_cec_set_divider()
52 u8 reg; in s5p_cec_enable_rx() local
54 reg = readb(cec->reg + S5P_CEC_RX_CTRL); in s5p_cec_enable_rx()
[all …]
/linux/drivers/scsi/qla2xxx/
H A Dqla_dbg.c107 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla27xx_dump_mpi_ram() local
118 if (qla_pci_disconnected(vha, reg)) in qla27xx_dump_mpi_ram()
125 wrt_reg_word(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM); in qla27xx_dump_mpi_ram()
126 wrt_reg_word(&reg->mailbox1, LSW(addr)); in qla27xx_dump_mpi_ram()
127 wrt_reg_word(&reg->mailbox8, MSW(addr)); in qla27xx_dump_mpi_ram()
129 wrt_reg_word(&reg->mailbox2, MSW(LSD(dump_dma))); in qla27xx_dump_mpi_ram()
130 wrt_reg_word(&reg->mailbox3, LSW(LSD(dump_dma))); in qla27xx_dump_mpi_ram()
131 wrt_reg_word(&reg->mailbox6, MSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram()
132 wrt_reg_word(&reg->mailbox7, LSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram()
134 wrt_reg_word(&reg->mailbox4, MSW(dwords)); in qla27xx_dump_mpi_ram()
[all …]
/linux/arch/riscv/include/asm/
H A Dgdb_xml.h26 "<reg name=\""DBG_REG_ZERO"\" bitsize=\"64\" type=\"int\" regnum=\"0\"/>"
27 "<reg name=\""DBG_REG_RA"\" bitsize=\"64\" type=\"code_ptr\"/>"
28 "<reg name=\""DBG_REG_SP"\" bitsize=\"64\" type=\"data_ptr\"/>"
29 "<reg name=\""DBG_REG_GP"\" bitsize=\"64\" type=\"data_ptr\"/>"
30 "<reg name=\""DBG_REG_TP"\" bitsize=\"64\" type=\"data_ptr\"/>"
31 "<reg name=\""DBG_REG_T0"\" bitsize=\"64\" type=\"int\"/>"
32 "<reg name=\""DBG_REG_T1"\" bitsize=\"64\" type=\"int\"/>"
33 "<reg name=\""DBG_REG_T2"\" bitsize=\"64\" type=\"int\"/>"
34 "<reg name=\""DBG_REG_FP"\" bitsize=\"64\" type=\"data_ptr\"/>"
35 "<reg name=\""DBG_REG_S1"\" bitsize=\"64\" type=\"int\"/>"
[all …]
/linux/drivers/video/fbdev/riva/
H A Dnvreg.h44 #define DEVICE_ACCESS(device,reg) \ argument
45 nvCONTROL[(NV_##device##_##reg)/4]
47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument
48 #define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) argument
49 #define DEVICE_PRINT(device,reg) \ argument
50 ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg))
56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument
57 #define PDAC_Read(reg) DEVICE_READ(PDAC,reg) argument
58 #define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg) argument
63 #define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) argument
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15_common.h36 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) argument
37 #define SOC15_REG_OFFSET1(ip, inst, reg, offset) \ argument
38 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset))
40 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \ argument
42 amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \
43 WREG32(reg, value))
45 #define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \ argument
47 amdgpu_sriov_rreg(adev, reg, flag, hwip, inst) : \
48 RREG32(reg))
50 #define WREG32_FIELD15(ip, idx, reg, field, val) \ argument
[all …]
/linux/tools/perf/arch/csky/util/
H A Dunwind-libdw.c16 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
23 dwarf_regs[0] = REG(A0); in libdw__arch_set_initial_registers()
24 dwarf_regs[1] = REG(A1); in libdw__arch_set_initial_registers()
25 dwarf_regs[2] = REG(A2); in libdw__arch_set_initial_registers()
26 dwarf_regs[3] = REG(A3); in libdw__arch_set_initial_registers()
27 dwarf_regs[4] = REG(REGS0); in libdw__arch_set_initial_registers()
28 dwarf_regs[5] = REG(REGS1); in libdw__arch_set_initial_registers()
29 dwarf_regs[6] = REG(REGS2); in libdw__arch_set_initial_registers()
30 dwarf_regs[7] = REG(REGS3); in libdw__arch_set_initial_registers()
31 dwarf_regs[8] = REG(REGS in libdw__arch_set_initial_registers()
[all...]
/linux/drivers/media/platform/nxp/imx-jpeg/
H A Dmxc-jpeg-hw.c18 dev_dbg(dev, "Wrapper reg %s = 0x%x\n", reg_name, val);\
35 void print_cast_status(struct device *dev, void __iomem *reg, in print_cast_status() argument
39 print_wrapper_reg(dev, reg, CAST_STATUS0); in print_cast_status()
40 print_wrapper_reg(dev, reg, CAST_STATUS1); in print_cast_status()
41 print_wrapper_reg(dev, reg, CAST_STATUS2); in print_cast_status()
42 print_wrapper_reg(dev, reg, CAST_STATUS3); in print_cast_status()
43 print_wrapper_reg(dev, reg, CAST_STATUS4); in print_cast_status()
44 print_wrapper_reg(dev, reg, CAST_STATUS5); in print_cast_status()
45 print_wrapper_reg(dev, reg, CAST_STATUS6); in print_cast_status()
46 print_wrapper_reg(dev, reg, CAST_STATUS7); in print_cast_status()
[all …]
/linux/drivers/net/ethernet/microchip/
H A Dencx24j600-regmap.c60 static int regmap_encx24j600_sfr_read(void *context, u8 reg, u8 *val, in regmap_encx24j600_sfr_read() argument
64 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_read()
65 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); in regmap_encx24j600_sfr_read()
71 if (reg < 0x80) { in regmap_encx24j600_sfr_read()
81 switch (reg) { in regmap_encx24j600_sfr_read()
104 tx_buf[i++] = reg; in regmap_encx24j600_sfr_read()
112 u8 reg, u8 *val, size_t len, in regmap_encx24j600_sfr_update() argument
115 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_update()
116 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); in regmap_encx24j600_sfr_update()
120 { .tx_buf = &reg, .len = sizeof(reg), }, in regmap_encx24j600_sfr_update()
[all …]
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2400pci.c48 u32 reg; in rt2400pci_bbp_write() local
56 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { in rt2400pci_bbp_write()
57 reg = 0; in rt2400pci_bbp_write()
58 rt2x00_set_field32(&reg, BBPCSR_VALUE, value); in rt2400pci_bbp_write()
59 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word); in rt2400pci_bbp_write()
60 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1); in rt2400pci_bbp_write()
61 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1); in rt2400pci_bbp_write()
63 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_write()
72 u32 reg; in rt2400pci_bbp_read() local
82 * doesn't become available in time, reg will be 0xffffffff in rt2400pci_bbp_read()
[all …]
H A Drt2500pci.c48 u32 reg; in rt2500pci_bbp_write() local
56 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { in rt2500pci_bbp_write()
57 reg = 0; in rt2500pci_bbp_write()
58 rt2x00_set_field32(&reg, BBPCSR_VALUE, value); in rt2500pci_bbp_write()
59 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word); in rt2500pci_bbp_write()
60 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1); in rt2500pci_bbp_write()
61 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1); in rt2500pci_bbp_write()
63 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2500pci_bbp_write()
72 u32 reg; in rt2500pci_bbp_read() local
82 * doesn't become available in time, reg will be 0xffffffff in rt2500pci_bbp_read()
[all …]
H A Drt61pci.c57 u32 reg; in rt61pci_bbp_write() local
65 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { in rt61pci_bbp_write()
66 reg = 0; in rt61pci_bbp_write()
67 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value); in rt61pci_bbp_write()
68 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word); in rt61pci_bbp_write()
69 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1); in rt61pci_bbp_write()
70 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0); in rt61pci_bbp_write()
72 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); in rt61pci_bbp_write()
81 u32 reg; in rt61pci_bbp_read() local
91 * doesn't become available in time, reg will be 0xffffffff in rt61pci_bbp_read()
[all …]
/linux/drivers/clk/imx/
H A Dclk.h107 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ argument
109 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
115 #define imx_clk_pfd(name, parent_name, reg, idx) \ argument
116 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
118 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ argument
119 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
127 #define imx_clk_divider(name, parent, reg, shift, width) \ argument
128 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
130 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \ argument
131 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dmcs.c29 u64 reg; in mcs_get_tx_secy_stats() local
31 reg = MCSX_CSE_TX_MEM_SLAVE_IFOUTCTLBCPKTSX(id); in mcs_get_tx_secy_stats()
32 stats->ctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
34 reg = MCSX_CSE_TX_MEM_SLAVE_IFOUTCTLMCPKTSX(id); in mcs_get_tx_secy_stats()
35 stats->ctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
37 reg = MCSX_CSE_TX_MEM_SLAVE_IFOUTCTLOCTETSX(id); in mcs_get_tx_secy_stats()
38 stats->ctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
40 reg = MCSX_CSE_TX_MEM_SLAVE_IFOUTCTLUCPKTSX(id); in mcs_get_tx_secy_stats()
41 stats->ctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
43 reg = MCSX_CSE_TX_MEM_SLAVE_IFOUTUNCTLBCPKTSX(id); in mcs_get_tx_secy_stats()
[all …]
/linux/drivers/clk/
H A Dclk-highbank.c39 void __iomem *reg; member
46 u32 reg; in clk_pll_prepare() local
48 reg = readl(hbclk->reg); in clk_pll_prepare()
49 reg &= ~HB_PLL_RESET; in clk_pll_prepare()
50 writel(reg, hbclk->reg); in clk_pll_prepare()
52 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) in clk_pll_prepare()
54 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) in clk_pll_prepare()
63 u32 reg; in clk_pll_unprepare() local
65 reg = readl(hbclk->reg); in clk_pll_unprepare()
66 reg |= HB_PLL_RESET; in clk_pll_unprepare()
[all …]
/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_dcb_82598.c21 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82598() local
26 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; in ixgbe_dcb_config_rx_arbiter_82598()
27 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); in ixgbe_dcb_config_rx_arbiter_82598()
29 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); in ixgbe_dcb_config_rx_arbiter_82598()
31 reg &= ~IXGBE_RMCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82598()
33 reg |= IXGBE_RMCS_RRM; in ixgbe_dcb_config_rx_arbiter_82598()
35 reg |= IXGBE_RMCS_DFP; in ixgbe_dcb_config_rx_arbiter_82598()
37 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); in ixgbe_dcb_config_rx_arbiter_82598()
44 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); in ixgbe_dcb_config_rx_arbiter_82598()
47 reg |= IXGBE_RT2CR_LSP; in ixgbe_dcb_config_rx_arbiter_82598()
[all …]
/linux/drivers/memory/tegra/
H A Dtegra210.c21 .reg = 0x228,
25 .reg = 0x2e8,
37 .reg = 0x228,
41 .reg = 0x2f4,
53 .reg = 0x228,
57 .reg = 0x2e8,
69 .reg = 0x228,
73 .reg = 0x2f4,
85 .reg = 0x228,
89 .reg = 0x2ec,
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-fau.h123 * @reg: FAU atomic register to access. 0 <= reg < 2048.
129 static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg) in __cvmx_fau_store_address() argument
133 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); in __cvmx_fau_store_address()
143 * @reg: FAU atomic register to access. 0 <= reg < 2048.
152 static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, in __cvmx_fau_atomic_address() argument
158 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); in __cvmx_fau_atomic_address()
164 * @reg: FAU atomic register to access. 0 <= reg < 2048.
170 static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, in cvmx_fau_fetch_and_add64() argument
173 return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value)); in cvmx_fau_fetch_and_add64()
179 * @reg: FAU atomic register to access. 0 <= reg < 2048.
[all …]
/linux/drivers/staging/media/sunxi/cedrus/
H A Dcedrus_mpeg2.c19 u32 reg; in cedrus_mpeg2_irq_status() local
21 reg = cedrus_read(dev, VE_DEC_MPEG_STATUS); in cedrus_mpeg2_irq_status()
22 reg &= VE_DEC_MPEG_STATUS_CHECK_MASK; in cedrus_mpeg2_irq_status()
24 if (!reg) in cedrus_mpeg2_irq_status()
27 if (reg & VE_DEC_MPEG_STATUS_CHECK_ERROR || in cedrus_mpeg2_irq_status()
28 !(reg & VE_DEC_MPEG_STATUS_SUCCESS)) in cedrus_mpeg2_irq_status()
44 u32 reg = cedrus_read(dev, VE_DEC_MPEG_CTRL); in cedrus_mpeg2_irq_disable() local
46 reg &= ~VE_DEC_MPEG_CTRL_IRQ_MASK; in cedrus_mpeg2_irq_disable()
48 cedrus_write(dev, VE_DEC_MPEG_CTRL, reg); in cedrus_mpeg2_irq_disable()
61 u32 reg; in cedrus_mpeg2_setup() local
[all …]
/linux/drivers/media/pci/cx23885/
H A Dcx23885-ioctl.c32 struct v4l2_dbg_register *reg) in cx23417_g_register() argument
39 if ((reg->reg & 0x3) != 0 || reg->reg >= 0x10000) in cx23417_g_register()
42 if (mc417_register_read(dev, (u16) reg->reg, &value)) in cx23417_g_register()
45 reg->size = 4; in cx23417_g_register()
46 reg->val = value; in cx23417_g_register()
51 struct v4l2_dbg_register *reg) in cx23885_g_register() argument
55 if (reg->match.addr > 1) in cx23885_g_register()
57 if (reg->match.addr) in cx23885_g_register()
58 return cx23417_g_register(dev, reg); in cx23885_g_register()
60 if ((reg->reg & 0x3) != 0 || reg->reg >= pci_resource_len(dev->pci, 0)) in cx23885_g_register()
[all …]
/linux/arch/arm/boot/dts/aspeed/
H A Dibm-power11-quad.dtsi132 reg = <0 0>;
139 reg = <0x1000 0x400>;
144 reg = <0x1800 0x400>;
149 reg = <0>; /* OMI01 */
155 reg = <0x20>;
160 reg = <0 0>;
167 reg = <0x1000 0x400>;
172 reg = <0x2400 0x400>;
179 reg = <1>; /* OMI23 */
185 reg = <0x20>;
[all …]

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