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/linux/drivers/clk/imx/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/clk-provider.h>
107 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ argument
109 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
115 #define imx_clk_pfd(name, parent_name, reg, idx) \ argument
116 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
118 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ argument
119 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
127 #define imx_clk_divider(name, parent, reg, shift, width) \ argument
128 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
[all …]
H A Dclk-divider-gate.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
32 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate_ro()
33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro()
37 return divider_recalc_rate(hw, parent_rate, val, div->table, in clk_divider_gate_recalc_rate_ro()
38 div->flags, div->width); in clk_divider_gate_recalc_rate_ro()
49 spin_lock_irqsave(div->lock, flags); in clk_divider_gate_recalc_rate()
52 val = div_gate->cached_val; in clk_divider_gate_recalc_rate()
54 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate()
55 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate()
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/linux/arch/arm/boot/dts/ti/omap/
H A Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
13 reg = <0x4>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
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H A Domap2430-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-mux-clock";
13 reg = <0x78>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <2>;
27 reg = <0x78>;
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H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
[all …]
H A Domap2420-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-no-wait-gate-clock";
13 ti,bit-shift = <15>;
14 reg = <0x0070>;
18 #clock-cells = <0>;
19 compatible = "ti,composite-mux-clock";
21 ti,bit-shift = <8>;
22 reg = <0x0070>;
26 #clock-cells = <0>;
[all …]
H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
21 reg = <0x0108>;
[all …]
/linux/drivers/memory/tegra/
H A Dtegra114.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/memory/tegra114-mc.h>
20 .reg = 0x34c,
21 .shift = 0,
32 .reg = 0x228,
36 .reg = 0x2e8,
37 .shift = 0,
48 .reg = 0x228,
52 .reg = 0x2f4,
53 .shift = 0,
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H A Dtegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/memory/tegra124-mc.h>
21 .reg = 0x34c,
22 .shift = 0,
33 .reg = 0x228,
37 .reg = 0x2e8,
38 .shift = 0,
49 .reg = 0x228,
53 .reg = 0x2f4,
54 .shift = 0,
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H A Dtegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/memory/tegra30-mc.h>
42 .reg = 0x34c,
43 .shift = 0,
55 .reg = 0x228,
59 .reg = 0x2e8,
60 .shift = 0,
72 .reg = 0x228,
76 .reg = 0x2f4,
77 .shift = 0,
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/linux/drivers/bus/
H A Dda8xx-mstpri.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * some changes (as is the case for the LCD controller on da850-lcdk - the
54 int reg; member
55 int shift; member
61 .reg = DA8XX_MSTPRI0_OFFSET,
62 .shift = 0,
66 .reg = DA8XX_MSTPRI0_OFFSET,
67 .shift = 4,
71 .reg = DA8XX_MSTPRI0_OFFSET,
72 .shift = 16,
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/linux/drivers/clk/sunxi-ng/
H A Dccu_mp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
13 static unsigned int next_div(unsigned int div, bool shift) in next_div() argument
15 if (shift) in next_div()
22 bool shift, in ccu_mp_find_best() argument
29 for (_p = 1; _p <= max_p; _p = next_div(_p, shift)) { in ccu_mp_find_best()
36 if ((rate - tmp_rate) < (rate - best_rate)) { in ccu_mp_find_best()
55 bool shift) in ccu_mp_find_best_with_parent_adj() argument
72 for (_p = 1; _p <= max_p; _p = next_div(_p, shift)) { in ccu_mp_find_best_with_parent_adj()
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/linux/drivers/regulator/
H A Dmax8998.c1 // SPDX-License-Identifier: GPL-2.0+
3 // max8998.c - Voltage regulator driver for the Maxim 8998
5 // Copyright (C) 2009-2010 Samsung Electronics
23 #include <linux/mfd/max8998-private.h>
44 int *reg, int *shift) in max8998_get_enable_register() argument
50 *reg = MAX8998_REG_ONOFF1; in max8998_get_enable_register()
51 *shift = 3 - (ldo - MAX8998_LDO2); in max8998_get_enable_register()
54 *reg = MAX8998_REG_ONOFF2; in max8998_get_enable_register()
55 *shift = 7 - (ldo - MAX8998_LDO6); in max8998_get_enable_register()
58 *reg = MAX8998_REG_ONOFF3; in max8998_get_enable_register()
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/linux/arch/arm/mach-omap2/
H A Dvp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 * struct omap_vp_ops - per-VP operations
36 * struct omap_vp_common - register data common to all VDDs
37 * @vpconfig_erroroffset_mask: ERROROFFSET bitmask in the PRM_VP*_CONFIG reg
38 * @vpconfig_errorgain_mask: ERRORGAIN bitmask in the PRM_VP*_CONFIG reg
39 * @vpconfig_initvoltage_mask: INITVOLTAGE bitmask in the PRM_VP*_CONFIG reg
40 * @vpconfig_timeouten: TIMEOUT bitmask in the PRM_VP*_CONFIG reg
41 * @vpconfig_initvdd: INITVDD bitmask in the PRM_VP*_CONFIG reg
42 * @vpconfig_forceupdate: FORCEUPDATE bitmask in the PRM_VP*_CONFIG reg
43 * @vpconfig_vpenable: VPENABLE bitmask in the PRM_VP*_CONFIG reg
[all …]
/linux/drivers/clk/
H A Dclk-axm5516.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/clk-axm5516.c
16 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/lsi,axm5516-clks.h>
22 * struct axxia_clk - Common struct to all Axxia clocks.
33 * struct axxia_pllclk - Axxia PLL generated clock.
35 * @reg: Offset into regmap for PLL control register
39 u32 reg; member
44 * axxia_pllclk_recalc - Calculate the PLL generated clock rate given the
55 regmap_read(aclk->regmap, pll->reg, &control); in axxia_pllclk_recalc()
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/linux/sound/soc/codecs/
H A Dpcm6240.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2022 - 2024 Texas Instruments Incorporated
12 // Author: Shenghao Ding <shenghao-ding@ti.com>
63 .shift = 1,
64 .reg = ADC5120_REG_CH1_ANALOG_GAIN,
69 .shift = 1,
70 .reg = ADC5120_REG_CH2_ANALOG_GAIN,
78 .shift
542 pcmdev_dev_read(struct pcmdevice_priv * pcm_dev,unsigned int dev_no,unsigned int reg,unsigned int * val) pcmdev_dev_read() argument
567 pcmdev_dev_update_bits(struct pcmdevice_priv * pcm_dev,unsigned int dev_no,unsigned int reg,unsigned int mask,unsigned int value) pcmdev_dev_update_bits() argument
604 unsigned int shift = mc->shift; pcmdev_get_volsw() local
605 unsigned int reg = mc->reg; pcmdev_get_volsw() local
677 unsigned int shift = mc->shift; pcmdev_put_volsw() local
679 unsigned int reg = mc->reg; pcmdev_put_volsw() local
1087 pcmdev_dev_bulk_write(struct pcmdevice_priv * pcm_dev,unsigned int dev_no,unsigned int reg,unsigned char * data,unsigned int len) pcmdev_dev_bulk_write() argument
1114 pcmdev_dev_write(struct pcmdevice_priv * pcm_dev,unsigned int dev_no,unsigned int reg,unsigned int value) pcmdev_dev_write() argument
[all...]
/linux/arch/arm64/lib/
H A Dinsn.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com>
15 #include <asm/debug-monitors.h>
28 int shift; in aarch64_get_imm_shift_mask() local
32 mask = BIT(26) - 1; in aarch64_get_imm_shift_mask()
33 shift = 0; in aarch64_get_imm_shift_mask()
36 mask = BIT(19) - 1; in aarch64_get_imm_shift_mask()
37 shift = 5; in aarch64_get_imm_shift_mask()
40 mask = BIT(16) - 1; in aarch64_get_imm_shift_mask()
41 shift = 5; in aarch64_get_imm_shift_mask()
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/linux/drivers/clk/meson/
H A Dparm.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 #define PMASK(width) GENMASK(width - 1, 0)
14 #define SETPMASK(width, shift) GENMASK(shift + width - 1, shift) argument
15 #define CLRPMASK(width, shift) (~SETPMASK(width, shift)) argument
17 #define PARM_GET(width, shift, reg) \ argument
18 (((reg) & SETPMASK(width, shift)) >> (shift))
19 #define PARM_SET(width, shift, reg, val) \ argument
20 (((reg) & CLRPMASK(width, shift)) | ((val) << (shift)))
22 #define MESON_PARM_APPLICABLE(p) (!!((p)->width))
26 u8 shift; member
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H A Ds4-pll.c1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
5 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
9 #include <linux/clk-provider.h>
13 #include "clk-mpll.h"
14 #include "clk-pll.h"
15 #include "clk-regmap.h"
16 #include "meson-clkc-utils.h"
17 #include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
50 * in the kernel phase. Write of fixed PLL-related register will cause the system to crash.
58 .shift = 28,
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/linux/sound/soc/sprd/
H A Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
118 static void sprd_mcdt_update(struct sprd_mcdt_dev *mcdt, u32 reg, u32 val, in sprd_mcdt_update() argument
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
125 writel_relaxed(tmp, mcdt->base + reg); in sprd_mcdt_update()
131 u32 reg = MCDT_DAC0_WTMK + channel * 4; in sprd_mcdt_dac_set_watermark() local
136 sprd_mcdt_update(mcdt, reg, water_mark, in sprd_mcdt_dac_set_watermark()
143 u32 reg = MCDT_ADC0_WTMK + channel * 4; in sprd_mcdt_adc_set_watermark() local
148 sprd_mcdt_update(mcdt, reg, water_mark, in sprd_mcdt_adc_set_watermark()
155 u32 shift = MCDT_DAC_DMA_SHIFT + channel; in sprd_mcdt_dac_dma_enable() local
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/linux/sound/pci/ac97/
H A Dac97_patch.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 #define AC97_SINGLE_VALUE(reg,shift,mask,invert) \ argument
11 ((reg) | ((shift) << 8) | ((shift) << 12) | ((mask) << 16) | \
13 #define AC97_PAGE_SINGLE_VALUE(reg,shift,mask,invert,page) \ argument
14 (AC97_SINGLE_VALUE(reg,shift,mask,invert) | (1<<25) | ((page) << 26))
15 #define AC97_SINGLE(xname, reg, shift, mask, invert) \ argument
19 .private_value = AC97_SINGLE_VALUE(reg, shift, mask, invert) }
20 #define AC97_PAGE_SINGLE(xname, reg, shift, mask, invert, page) \ argument
24 .private_value = AC97_PAGE_SINGLE_VALUE(reg, shift, mask, invert, page) }
25 #define AC97_DOUBLE(xname, reg, shift_left, shift_right, mask, invert) \ argument
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/linux/drivers/clk/x86/
H A Dclk-cgu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
8 #include <linux/clk-provider.h>
12 #include "clk-cgu.h"
14 #define GATE_HW_REG_STAT(reg) ((reg) + 0x0) argument
15 #define GATE_HW_REG_EN(reg) ((reg) + 0x4) argument
16 #define GATE_HW_REG_DIS(reg) ((reg) + 0x8) argument
29 if (list->div_flags & CLOCK_FLAG_VAL_INIT) in lgm_clk_register_fixed()
30 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed()
31 list->div_width, list->div_val); in lgm_clk_register_fixed()
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/linux/drivers/clk/mxs/
H A Dclk-frac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
13 * struct clk_frac - mxs fractional divider clock
15 * @reg: register address
16 * @shift: the divider bit shift
18 * @busy: busy bit shift
25 void __iomem *reg; member
26 u8 shift; member
40 div = readl_relaxed(frac->reg) >> frac->shift; in clk_frac_recalc_rate()
41 div &= (1 << frac->width) - 1; in clk_frac_recalc_rate()
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/linux/drivers/clk/rockchip/
H A Dclk-gate-grf.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk-provider.h>
20 unsigned int reg; member
21 unsigned int shift; member
30 u32 val = !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? BIT(gate->shift) : 0; in rockchip_gate_grf_enable()
31 u32 hiword = ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->shift + 16); in rockchip_gate_grf_enable()
34 ret = regmap_update_bits(gate->regmap, gate->reg, in rockchip_gate_grf_enable()
35 hiword | BIT(gate->shift), hiword | val); in rockchip_gate_grf_enable()
43 u32 val = !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : BIT(gate->shift); in rockchip_gate_grf_disable()
44 u32 hiword = ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->shift + 16); in rockchip_gate_grf_disable()
[all …]
H A Dclk-inverter.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
15 void __iomem *reg; member
16 int shift; member
30 val = readl(inv_clock->reg) >> inv_clock->shift; in rockchip_inv_get_phase()
45 return -EINVAL; in rockchip_inv_set_phase()
48 if (inv_clock->flags & ROCKCHIP_INVERTER_HIWORD_MASK) { in rockchip_inv_set_phase()
49 writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift), in rockchip_inv_set_phase()
50 inv_clock->reg); in rockchip_inv_set_phase()
53 u32 reg; in rockchip_inv_set_phase() local
[all …]

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