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Searched full:refin (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/clk/sprd/
H A Dpll.c72 const unsigned long refin[4] = { 2, 4, 13, 26 }; in pll_get_refin() local
83 return refin[refin_id]; in pll_get_refin()
104 u64 refin; in _sprd_pll_recalc_rate() local
114 refin = pll_get_refin(pll); in _sprd_pll_recalc_rate()
117 refin = refin * 2; in _sprd_pll_recalc_rate()
122 refin = refin / 2; in _sprd_pll_recalc_rate()
125 rate = refin * pinternal_val(pll, cfg, PLL_N) * CLK_PLL_10M; in _sprd_pll_recalc_rate()
135 rate = DIV_ROUND_CLOSEST_ULL(refin * kint * k1, in _sprd_pll_recalc_rate()
137 k2 + refin * nint * CLK_PLL_1M; in _sprd_pll_recalc_rate()
156 u64 tmp, refin, fvco = rate; in _sprd_pll_set_rate() local
[all …]
H A Dsc9860-clk.c131 { .shift = 0, .width = 0 }, /* refin */
148 { .shift = 0, .width = 0 }, /* refin */
164 { .shift = 0, .width = 0 }, /* refin */
183 { .shift = 0, .width = 0 }, /* refin */
202 { .shift = 0, .width = 0 }, /* refin */
218 { .shift = 0, .width = 0 }, /* refin */
238 { .shift = 0, .width = 0 }, /* refin */
255 { .shift = 0, .width = 0 }, /* refin */
H A Dsc9863a-clk.c83 { .shift = 0, .width = 0 }, /* refin */
118 { .shift = 0, .width = 0 }, /* refin */
136 { .shift = 0, .width = 0 }, /* refin */
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dadi,ad4170-4.yaml59 description: REFIN+ supply that can be used as reference for conversion.
62 description: REFIN- supply that can be used as reference for conversion.
206 25: REFIN+
207 26: REFIN-
221 0: REFIN+/REFIN-
530 // Sample AIN6 with respect to 2.5V throughout REFIN+/REFIN- input range
H A Dadi,ad7923.yaml43 refin-supply:
76 refin-supply = <&adc_vref>;
H A Dadi,max14001.yaml45 refin-supply:
/linux/Documentation/devicetree/bindings/iio/addac/
H A Dadi,ad74413r.yaml47 refin-supply: true
62 - refin-supply
143 refin-supply = <&ad74413r_refin>;
H A Dadi,ad74115.yaml54 refin-supply: true
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-frequency-adf435015 Sets channel Y REFin frequency in Hz. In some clock chained
21 down the PLL and its RFOut buffers during REFin changes.
/linux/Documentation/iio/
H A Dad7380.rst52 declared in the device tree as ``refin-supply``.
57 ad7389-4 supports only an internal reference voltage. ``refin-supply`` and
64 derived from one of its supplies (``refin-supply``)
H A Dad7606.rst138 The source is determined by the device tree. If ``refin-supply`` is present,
/linux/drivers/iio/adc/
H A Dad7944.c698 * - internal reference: neither REF or REFIN is connected in ad7944_probe()
699 * - internal reference with external buffer: REF not connected, REFIN in ad7944_probe()
701 * - external reference: REF is connected, REFIN is not connected in ad7944_probe()
710 ret = devm_regulator_get_enable_optional(dev, "refin"); in ad7944_probe()
712 return dev_err_probe(dev, ret, "failed to get REFIN voltage\n"); in ad7944_probe()
718 "cannot have both refin and ref supplies\n"); in ad7944_probe()
H A Dmax14001.c328 ret = devm_regulator_get_enable_read_voltage(dev, "refin"); in max14001_probe()
330 return dev_err_probe(dev, ret, "Failed to get REFIN voltage\n"); in max14001_probe()
347 "Failed to set External REFIN in Configuration Register\n"); in max14001_probe()
H A Dad7923.c28 #define AD7923_RANGE BIT(1) /* range to REFin */
342 st->reg = devm_regulator_get(&spi->dev, "refin"); in ad7923_probe()
H A Dad4030.c920 /* if not using optional REF, the REFIN must be used */ in ad4030_regulators_get()
922 "refin"); in ad4030_regulators_get()
925 "Failed to read refin voltage\n"); in ad4030_regulators_get()
H A Dad7380.c508 "ldo", "vcc", "vlogic", "vs-p", "vs-n", "refin",
1902 * "refin" is already enabled with other power supplies in ad7380_probe()
1911 ret = devm_regulator_get_enable_read_voltage(dev, "refin"); in ad7380_probe()
1914 "Failed to get refin regulator\n"); in ad7380_probe()
H A Dad7791.c426 st->reg = devm_regulator_get(&spi->dev, "refin"); in ad7791_probe()
H A Dad4695.c1861 /* If REFIN supply is given, then we are using internal buffer */ in ad4695_probe()
1862 ret = devm_regulator_get_enable_read_voltage(dev, "refin"); in ad4695_probe()
1864 return dev_err_probe(dev, ret, "Failed to get REFIN voltage\n"); in ad4695_probe()
H A Dad7606.c1529 ret = devm_regulator_get_enable_optional(dev, "refin"); in ad7606_probe()
1532 "Failed to enable REFIN supply\n"); in ad7606_probe()
/linux/drivers/gpu/drm/sprd/
H A Dsprd_dsi.h68 u8 refin; /* Pre-divider control signal */ member
H A Dmegacores_pll.c72 pll->refin = 3; /* pre-divider bypass */ in dphy_calc_pll_param()
94 reg_val[3] = pll->vco_band | (pll->sdm_en << 1) | (pll->refin << 2); in dphy_set_pll_reg()
/linux/drivers/iio/frequency/
H A Dadf4371.c538 * fPFD = REFIN × ((1 + D)/(R × (1 + T))) in adf4371_setup()
539 * Where D is the REFIN doubler bit, T is the reference divide by 2, in adf4371_setup()
/linux/drivers/iio/addac/
H A Dad74413r.c1377 ret = devm_regulator_get_enable_read_voltage(st->dev, "refin"); in ad74413r_probe()
1380 "Failed to get refin regulator voltage\n"); in ad74413r_probe()
H A Dad74115.c1824 "avcc", "dvcc", "dovdd", "refin", in ad74115_probe()
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-pko-defs.h1477 uint64_t refin:1; member
1479 uint64_t refin:1;