| /linux/drivers/video/fbdev/kyro/ |
| H A D | STG4000InitDevice.c | 117 u32 ProgramClock(u32 refClock, in ProgramClock() argument
131 refClock *= 1000; /* in Hz */ in ProgramClock()
153 F = (u32)(ulTmp / (refClock >> STG4K3_PLL_SCALER)); in ProgramClock()
168 ulVCO = refClock / R; in ProgramClock()
186 …ulPhaseScore = (((refClock / R) - (refClock / STG4K3_PLL_MAX_R))) / ((refClock - (refClock / STG4K… in ProgramClock()
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| H A D | STG4000Interface.h | 37 extern u32 ProgramClock(u32 refClock, u32 coreClock, u32 *FOut, u32 *ROut, u32 *POut);
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | fsl,imx8-pcie-phy.yaml | 46 refclock is derived from SoC internal source), INPUT(PHY refclock
47 is provided externally via the refclk pad) or OUTPUT(PHY refclock
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| H A D | fsl,imx8qm-hsio.yaml | 69 Specifies the mode of the refclk pad used. INPUT(PHY refclock is
70 provided externally via the refclk pad) or OUTPUT(PHY refclock is
72 This property not exists means unused(PHY refclock is derived from
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| H A D | ti,phy-j721e-wiz.yaml | 147 WIZ node should have subnodes for each of the PMA common refclock
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| /linux/drivers/media/tuners/ |
| H A D | mt2063.h | 9 u32 refclock; member
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| /linux/Documentation/devicetree/bindings/rtc/ |
| H A D | cdns,rtc.txt | 21 clocks = <&sysclock>, <&refclock>;
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| /linux/include/linux/ |
| H A D | mc146818rtc.h | 77 * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
82 /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
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| /linux/drivers/media/dvb-frontends/ |
| H A D | stb6100.h | 68 u32 refclock; member
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| H A D | stv6110x.c | 231 static int stv6110x_set_refclock(struct dvb_frontend *fe, u32 refclock) in stv6110x_set_refclock() argument
236 switch (refclock) { in stv6110x_set_refclock()
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| H A D | stb6100.c | 544 state->reference = config->refclock / 1000; /* kHz */ in stb6100_attach()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| H A D | dcn35_dccg.c | 501 /* DSCCLK#_EN=0 switches to refclock from functional clock */ in dccg35_set_dsc_clk_src_new()
629 /* If DTBCLK_P#_EN is 0 refclock is selected as functional clock in dccg35_set_dtbclk_p_src_new()
948 /* Switch from functional clock to refclock */ in dccg35_disable_symclk_be_new()
995 /* Switch from functional clock to refclock */ in dccg35_disable_symclk32_le_new()
2131 * Since clock source is not passed restore to refclock on ungate in dccg35_set_dpstreamclk_root_clock_gating_cb()
2190 * Since clock source is not passed restore to refclock on ungate in dccg35_dpp_root_clock_control_cb()
2231 * Since clock source is not passed restore to refclock on ungate in dccg35_set_symclk32_le_root_clock_gating_cb()
2274 * Since clock source is not passed restore to refclock on ungate in dccg35_set_symclk32_le_root_clock_gating()
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| /linux/drivers/phy/freescale/ |
| H A D | phy-fsl-imx8m-pcie.c | 103 /* Configure the PHY to output the refclock via pad */ in imx8_pcie_phy_power_on()
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| /linux/drivers/media/pci/mantis/ |
| H A D | mantis_vp1041.c | 293 .refclock = 27000000,
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| /linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-pcie2.c | 81 /* Don't use PAD for refclock */ in qcom_pcie2_phy_power_on()
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| /linux/drivers/usb/dwc3/ |
| H A D | dwc3-pci.c | 242 /* On BYT the FW does not always enable the refclock */ in dwc3_pci_quirks()
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| /linux/drivers/media/pci/ttpci/ |
| H A D | budget-ci.c | 1297 .refclock = 27000000,
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| /linux/drivers/phy/cadence/ |
| H A D | phy-cadence-torrent.c | 742 /* Assumes 19.2 MHz refclock */ in cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz()
862 /* Assumes 25 MHz refclock */ in cdns_torrent_dp_pma_cmn_vco_cfg_25mhz()
966 /* Assumes 100 MHz refclock */ in cdns_torrent_dp_pma_cmn_vco_cfg_100mhz()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| H A D | ramgk104.c | 1074 " (refclock: %i kHz)\n", next->freq, ret); in gk104_ram_calc_xits()
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| /linux/drivers/pci/controller/ |
| H A D | pci-tegra.c | 928 * Set up PHY PLL inputs select PLLE output as refclock, in tegra_pcie_phy_enable()
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| /linux/drivers/video/fbdev/ |
| H A D | cirrusfb.c | 852 /* hardware RefClock: 14.31818 MHz */ in cirrusfb_set_par_foo()
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| /linux/drivers/gpu/drm/amd/include/ |
| H A D | atombios.h | 1928 // bit[4]= RefClock source for PPLL.
1976 // bit[4]= RefClock source for PPLL.
2025 // bit[5:4]= RefClock source for PPLL.
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | atombios.h | 1652 // bit[4]= RefClock source for PPLL.
1700 // bit[4]= RefClock source for PPLL.
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