| /linux/Documentation/infiniband/ |
| H A D | tag_matching.rst | 14 The ordering rules require that when more than one pair of send and receive
16 and the earliest posted-receive is the pair that must be used to satisfy the
23 corresponding matching receive is posted. If a matching receive is posted,
44 There are two types of matching objects used, the posted receive list and the
45 unexpected message list. The application posts receive buffers through calls
46 to the MPI receive routines in the posted receive list and posts send messages
47 using the MPI send routines. The head of the posted receive list may be
50 When send is initiated and arrives at the receive side, if there is no
51 pre-posted receive for this arriving message, it is passed to the software and
54 specified receive buffer. This allows overlapping receive-side MPI tag
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| /linux/drivers/net/ethernet/apple/ |
| H A D | bmac.h | 22 # define MIIBuffDisable 0x0008 /* MII receive buffer disable */
31 #define RXFIFOCSR 0x120 /* receive FIFO control */
47 #define RXPNTR 0x1b0 /* receive pointer */
52 # define RxFrameCntExp 0x00000002 /* Receive frame counter expired */
56 # define RxOverFlow 0x00000020 /* Receive FIFO overflow */
68 # define RxNoDescriptors 0x00020000 /* No more receive descriptors */
69 # define RxDMAError 0x00040000 /* Error during receive DMA */
70 # define RxDMALateErr 0x00080000 /* Receive DMA, data late */
71 # define RxParityErr 0x00100000 /* Parity error during receive DMA */
72 # define RxTagError 0x00200000 /* Tag error during receive DMA */
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| /linux/Documentation/networking/ |
| H A D | scaling.rst | 17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
24 RSS: Receive Side Scaling
27 Contemporary NICs support multiple receive and transmit descriptor queues
31 of logical flows. Packets for each flow are steered to a separate receive
33 generally known as “Receive-side Scaling” (RSS). The goal of RSS and
42 stores a queue number. The receive queue for a packet is determined
64 can be directed to their own receive queue. Such “n-tuple” filters can
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| H A D | oa-tc6-framework.rst | 59 receive (RX) chunks. Chunks in both transmit and receive directions may
69 In parallel, receive data chunks are received on MISO. Each receive data
71 The data footer indicates if there is receive frame data present within
184 NORX (Bit 29) - No Receive flag. The SPI host may set this bit to prevent
189 any receive frame data within the current chunk.
200 chunk payload. Note that the receive path is unaffected by
254 host will be sent as multiple receive data chunks. Each receive data
257 location of the receive frame data within the 64 bytes data chunk payload.
284 RCA (Bit 28..24) - Receive Chunks Available. The RCA field indicates to
285 the SPI host the minimum number of additional receive
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| H A D | strparser.rst | 17 The strparser works in one of two modes: receive callback or general
20 In receive callback mode, the strparser is called from the data_ready
33 functions, and a data_ready function for receive callback mode. The
48 socket associated with the stream parser for use with receive
101 maximum messages size is the limit of the receive socket
102 buffer and message timeout is the receive timeout for the socket.
144 zero) and the parser is in receive callback mode, then it will set
156 processing a timeout). In receive callback mode the default
165 by the lock callback. In receive callback mode the default
190 the TCP socket in receive callback mode. The stream parser may
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| /linux/drivers/net/ethernet/actions/ |
| H A D | owl-emac.h | 35 /* Transmit/receive poll demand registers */
41 /* Receive/transmit descriptor list base address registers */
51 #define OWL_EMAC_MSK_MAC_CSR5_RS GENMASK(19, 17) /* Receive process state */
53 #define OWL_EMAC_VAL_MAC_CSR5_RS_FDES 0x01 /* Fetching receive descriptor */
54 #define OWL_EMAC_VAL_MAC_CSR5_RS_CDES 0x05 /* Closing receive descriptor */
58 #define OWL_EMAC_BIT_MAC_CSR5_ERI BIT(14) /* Early receive interrupt */
61 #define OWL_EMAC_BIT_MAC_CSR5_RPS BIT(8) /* Receive process stopped */
62 #define OWL_EMAC_BIT_MAC_CSR5_RU BIT(7) /* Receive buffer unavailable */
63 #define OWL_EMAC_BIT_MAC_CSR5_RI BIT(6) /* Receive interrupt */
73 #define OWL_EMAC_BIT_MAC_CSR6_RA BIT(30) /* Receive all */
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| /linux/drivers/net/ethernet/amd/ |
| H A D | ariadne.h | 78 #define CSR18 0x1200 /* Current Receive Buffer Address */
79 #define CSR19 0x1300 /* Current Receive Buffer Address */
82 #define CSR22 0x1600 /* Next Receive Buffer Address */
83 #define CSR23 0x1700 /* Next Receive Buffer Address */
84 #define CSR24 0x1800 /* - Base Address of Receive Ring */
85 #define CSR25 0x1900 /* - Base Address of Receive Ring */
86 #define CSR26 0x1a00 /* Next Receive Descriptor Address */
87 #define CSR27 0x1b00 /* Next Receive Descriptor Address */
88 #define CSR28 0x1c00 /* Current Receive Descriptor Address */
89 #define CSR29 0x1d00 /* Current Receive Descriptor Address */
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| /linux/drivers/infiniband/hw/vmw_pvrdma/ |
| H A D | pvrdma_srq.c | 56 * pvrdma_query_srq - query shared receive queue
57 * @ibsrq: the shared receive queue to query
79 "could not query shared receive queue, error: %d\n", in pvrdma_query_srq()
92 * pvrdma_create_srq - create shared receive queue
93 * @ibsrq: the IB shared receive queue
94 * @init_attr: shared receive queue attributes
116 "no shared receive queue support for kernel client\n"); in pvrdma_create_srq()
122 "shared receive queue type %d not supported\n", in pvrdma_create_srq()
130 "shared receive queue size invalid\n"); in pvrdma_create_srq()
142 "create shared receive queue from user space\n"); in pvrdma_create_srq()
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| /linux/drivers/net/ethernet/stmicro/stmmac/ |
| H A D | dwmac_dma.h | 18 #define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */
95 #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
101 #define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
102 #define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
111 #define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
112 #define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
113 #define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
115 #define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
137 #define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
141 #define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
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| /linux/include/uapi/rdma/ |
| H A D | ib_user_mad.h | 56 * @status - 0 on successful receive, ETIMEDOUT if no response
59 * @timeout_ms - Milliseconds to wait for response (unset on receive)
62 * @qkey - Remote Q_Key to be sent with (unset on receive)
67 * @gid_index - Local GID index to send with (unset on receive)
99 * @status - 0 on successful receive, ETIMEDOUT if no response
102 * @timeout_ms - Milliseconds to wait for response (unset on receive)
105 * @qkey - Remote Q_Key to be sent with (unset on receive)
110 * @gid_index - Local GID index to send with (unset on receive)
173 * @method_mask - The caller will receive unsolicited MADs for any method
175 * @mgmt_class - Indicates which management class of MADs should be receive
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| /linux/drivers/net/ethernet/sun/ |
| H A D | sunhme.h | 37 #define GREG_STAT_RCNTEXP 0x00000002 /* Receive frame counter expired */
41 #define GREG_STAT_RFIFOVF 0x00000020 /* Receive FIFO overflow */
52 #define GREG_STAT_RXTOHOST 0x00010000 /* Moved from receive-FIFO to host memory */
53 #define GREG_STAT_NORXD 0x00020000 /* No more receive descriptors */
54 #define GREG_STAT_RXERR 0x00040000 /* Error during receive dma */
55 #define GREG_STAT_RXLATERR 0x00080000 /* Late error during receive dma */
56 #define GREG_STAT_RXPERR 0x00100000 /* Parity error during receive dma */
57 #define GREG_STAT_RXTERR 0x00200000 /* Tag error during receive dma */
74 #define GREG_IMASK_RCNTEXP 0x00000002 /* Receive frame counter expired */
78 #define GREG_IMASK_RFIFOVF 0x00000020 /* Receive FIFO overflow */
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| H A D | sunbmac.h | 16 #define GLOB_RSIZE 0x10UL /* Receive partition size */
30 #define GLOB_STAT_RX 0x00000004 /* BigMAC Receive IRQ */
63 #define CREG_STAT_RXIRQ 0x00000020 /* Receive Interrupt */
65 #define CREG_STAT_RXSMALL 0x00000008 /* Receive buffer too small */
66 #define CREG_STAT_RXLERR 0x00000004 /* Receive Late Error */
67 #define CREG_STAT_RXPERR 0x00000002 /* Receive Parity Error */
68 #define CREG_STAT_RXSERR 0x00000001 /* Receive SBUS Error ACK */
114 #define BMAC_RXPMAX 0x310UL /* Receive max pkt size */
115 #define BMAC_RXPMIN 0x314UL /* Receive min pkt size */
119 #define BMAC_FRCTR 0x324UL /* Receive frame receive counter */
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| /linux/drivers/net/ethernet/freescale/fman/ |
| H A D | fman_mac.h | 98 /* 10GEC, mEMAC Receive FIFO overflow interrupt */
100 /* 10GEC, mEMAC Receive frame ECC error interrupt */
102 /* 10GEC Receive jabber frame interrupt */
104 /* 10GEC Receive oversized frame interrupt */
106 /* 10GEC Receive runt frame interrupt */
108 /* 10GEC Receive fragment frame interrupt */
110 /* 10GEC Receive payload length error interrupt */
112 /* 10GEC Receive CRC error interrupt */
114 /* 10GEC Receive alignment error interrupt */
116 /* dTSEC Babbling receive error */
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| /linux/drivers/net/ethernet/moxa/ |
| H A D | moxart_ether.h | 48 #define RX_DESC0_ODD_NB 0x400000 /* receive odd nibbles */
49 #define RX_DESC0_LRS 0x10000000 /* last receive segment */
50 #define RX_DESC0_FRS 0x20000000 /* first receive segment */
122 #define NORXBUF BIT(1) /* receive buffer unavailable */
127 #define RPKT_SAV BIT(6) /* FIFO receive success */
128 #define RPKT_LOST_INT_STS BIT(7) /* FIFO full, receive failed */
172 #define RX_BROADPKT BIT(17) /* receive broadcast packets */
173 #define RX_MULTIPKT BIT(16) /* receive all multicast packets */
181 #define ENRX_IN_HALFTX BIT(6) /* enable receive in half duplex mode */
186 #define RDMA_EN BIT(1) /* enable receive DMA chan */
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| /linux/drivers/staging/greybus/ |
| H A D | log.c | 22 struct gb_log_send_log_request *receive; in gb_log_request_handler() local
31 if (op->request->payload_size < sizeof(*receive)) { in gb_log_request_handler()
33 op->request->payload_size, sizeof(*receive)); in gb_log_request_handler()
36 receive = op->request->payload; in gb_log_request_handler()
37 len = le16_to_cpu(receive->len); in gb_log_request_handler()
38 if (len != (op->request->payload_size - sizeof(*receive))) { in gb_log_request_handler()
40 (op->request->payload_size - sizeof(*receive))); in gb_log_request_handler()
54 receive->msg[len - 1] = '\0'; in gb_log_request_handler()
60 dev_dbg(dev, "%s", receive->msg); in gb_log_request_handler()
|
| /linux/Documentation/networking/device_drivers/can/freescale/ |
| H A D | flexcan.rst | 19 and i.MX53 SOCs) only receive RTR frames if the controller is
30 With the "rx-rtr" private flag the ability to receive RTR frames can
31 be waived at the expense of losing the ability to receive RTR
35 Receive RTR frames. (default)
37 The CAN controller can and will receive RTR frames.
39 On some IP cores the controller cannot receive RTR frames in the
45 Waive ability to receive RTR frames. (not supported on all IP cores)
|
| /linux/drivers/net/ethernet/freescale/ |
| H A D | gianfar.h | 599 u8 rq; /* Receive Queue index */
613 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
614 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
615 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
616 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
617 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
618 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
619 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
620 u32 rbyt; /* 0x.69c - Receive Byte Counter */
621 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */
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| H A D | fec.h | 37 #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */
43 #define FEC_R_CNTRL 0x084 /* Receive control reg */
59 #define FEC_R_BOUND 0x14c /* FIFO receive bound reg */
60 #define FEC_R_FSTART 0x150 /* FIFO receive start reg */
61 #define FEC_R_DES_START_1 0x160 /* Receive descriptor ring 1 */
63 #define FEC_R_BUFF_SIZE_1 0x168 /* Maximum receive buff ring1 size */
64 #define FEC_R_DES_START_2 0x16c /* Receive descriptor ring 2 */
66 #define FEC_R_BUFF_SIZE_2 0x174 /* Maximum receive buff ring2 size */
67 #define FEC_R_DES_START_0 0x180 /* Receive descriptor ring */
69 #define FEC_R_BUFF_SIZE_0 0x188 /* Maximum receive buff size */
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| /linux/include/net/caif/ |
| H A D | caif_layer.h | 118 * @receive: Packet receive function.
141 * layer->up->receive(layer->up, packet);
152 * receive() - Receive Function (non-blocking).
153 * Contract: Each layer must implement a receive function passing the
157 * called receive function. This means that the
159 * above layer using up->receive().
173 * @layr: Pointer to the current layer the receive function is
177 int (*receive)(struct cflayer *layr, struct cfpkt *cfpkt); member
200 * @layr: Pointer to the current layer the receive function
211 * @layr: Pointer to the current layer the receive function
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| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | mpic-msgr.txt | 25 - mpic-msgr-receive-mask: Specifies what registers in the containing block
26 are allowed to receive interrupts. The value is a bit mask where a set
27 bit at bit 'n' indicates that message register 'n' can receive interrupts.
50 // Message registers 0 and 2 in this block can receive interrupts on
53 mpic-msgr-receive-mask = <0x5>;
59 // Message registers 0 and 2 in this block can receive interrupts on
62 mpic-msgr-receive-mask = <0x5>;
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| /linux/Documentation/networking/device_drivers/ethernet/microsoft/ |
| H A D | netvsc.rst | 23 Receive Side Scaling
25 Hyper-V supports receive side scaling. For TCP & UDP, packets can
51 Generic Receive Offload, aka GRO
57 Large Receive Offload (LRO), or Receive Side Coalescing (RSC)
83 Receive Buffer
85 Packets are received into a receive area which is created when device
86 is probed. The receive area is broken into MTU sized chunks and each may
87 contain one or more packets. The number of receive sections may be changed
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| /linux/drivers/infiniband/hw/hfi1/ |
| H A D | netdev.h | 16 * struct hfi1_netdev_rxq - Receive Queue for HFI
20 * @rcd: ptr to receive context data
39 * @rx_napi: the dummy netdevice to support "polling" the receive contexts
41 * @rxq: pointer to dummy netdev receive queues.
42 * @num_rx_q: number of receive queues
46 * @enabled: atomic counter of netdevs enabling receive queues.
49 * When 0 receive queues will be freed.
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| /linux/drivers/net/ethernet/mellanox/mlxbf_gige/ |
| H A D | mlxbf_gige_rx.c | 3 /* Packet receive logic for Mellanox Gigabit Ethernet driver
40 /* Enable MAC receive filter mask for specified index */ in mlxbf_gige_enable_mac_rx_filter()
52 /* Disable MAC receive filter mask for specified index */ in mlxbf_gige_disable_mac_rx_filter()
112 /* Receive Initialization
115 * 3) Initializes each element of RX WQE array with a receive
118 * 5) Completes other misc receive initialization
140 * Each RX WQE is simply a receive buffer pointer, so walk in mlxbf_gige_rx_init()
186 /* Clear MLXBF_GIGE_INT_MASK 'receive pkt' bit to in mlxbf_gige_rx_init()
187 * indicate readiness to receive interrupts in mlxbf_gige_rx_init()
213 /* Receive Deinitialization
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| /linux/drivers/net/ethernet/oki-semi/pch_gbe/ |
| H A D | pch_gbe.h | 93 #define PCH_GBE_INT_RX_DMA_CMPLT 0x00000001 /* Receive DMA Transfer Complete */
94 #define PCH_GBE_INT_RX_VALID 0x00000002 /* MAC Normal Receive Complete */
95 #define PCH_GBE_INT_RX_FRAME_ERR 0x00000004 /* Receive frame error */
96 #define PCH_GBE_INT_RX_FIFO_ERR 0x00000008 /* Receive FIFO Overflow */
97 #define PCH_GBE_INT_RX_DMA_ERR 0x00000010 /* Receive DMA Transfer Error */
98 #define PCH_GBE_INT_RX_DSC_EMP 0x00000020 /* Receive Descriptor Empty */
128 #define PCH_GBE_MRE_MAC_RX_EN 0x00000001 /* MAC Receive Enable */
140 /* Receive Almost Empty Threshold */
145 /* Receive Almost Full Threshold */
160 /* Receive Descriptor bit definitions */
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| /linux/include/linux/ |
| H A D | atmel-ssc.h | 50 /* SSC Receive Clock Mode Register */
69 /* SSC Receive Frame Mode Register */
134 /* SSC Receive Hold Register */
144 /* SSC Receive Sync. Holding Register */
154 /* SSC Receive Compare 0 Register */
159 /* SSC Receive Compare 1 Register */
276 /* SSC PDC Receive Pointer Register */
279 /* SSC PDC Receive Counter Register */
285 /* SSC PDC Receive Next Pointer Register */
288 /* SSC PDC Receive Next Counter Register */
|