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/linux/include/soc/at91/
H A Dat91sam9_ddrsdr.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
48 #define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Onl…
51 #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
52 #define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
53 #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
54 #define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
55 #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
57 #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
58 #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Darm,pl172.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl172.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
18 - arm,pl172
19 - arm,pl175
20 - arm,pl176
22 - compatible
27 - enum:
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H A Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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H A Dmvebu-devbus.txt9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
35 Read parameters:
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/linux/drivers/iio/common/ms_sensors/
H A Dms_sensors_i2c.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2015 Measurement-Specialties
11 #include <linux/delay.h>
38 * ms_sensors_reset() - Reset function
41 * @delay: usleep minimal delay after reset command is issued
47 int ms_sensors_reset(void *cli, u8 cmd, unsigned int delay) in ms_sensors_reset() argument
54 dev_err(&client->dev, "Failed to reset device\n"); in ms_sensors_reset()
57 usleep_range(delay, delay + 1000); in ms_sensors_reset()
64 * ms_sensors_read_prom_word() - PROM word read function
66 * @cmd: PROM read cmd. Depends on device and prom id
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/linux/arch/powerpc/platforms/pasemi/
H A Dgpio_mdio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2007 PA Semi, Inc
9 * Based on drivers/net/fs_enet/mii-bitbang.c.
25 #define DELAY 1 macro
34 #define MDC_PIN(bus) (((struct gpio_priv *)bus->priv)->mdc_pin)
35 #define MDIO_PIN(bus) (((struct gpio_priv *)bus->priv)->mdio_pin)
78 udelay(DELAY); in clock_out()
80 udelay(DELAY); in clock_out()
84 /* Utility to send the preamble, address, and register (common to read and write). */
85 static void bitbang_pre(struct mii_bus *bus, int read, u8 addr, u8 reg) in bitbang_pre() argument
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/linux/arch/sh/include/mach-common/mach/
H A Dsh2007.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 /* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */
28 /* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
31 /* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
34 /* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
37 /* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
40 /* burst count (0-3:4,8,16,32) */
46 /* RD hold for SRAM (0-1:0,1) */
49 /* Burst pitch (0-7:0,1,2,3,4,5,6,7) */
52 /* Multiplex (0-1:0,1) */
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/linux/drivers/md/
H A Ddm-delay.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2005-2007 Red Hat GmbH
17 #include <linux/delay.h>
19 #include <linux/device-mapper.h>
21 #define DM_MSG_PREFIX "delay"
28 unsigned int delay; member
43 struct delay_class read; member
61 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
66 timer_reduce(&dc->delay_timer, expires); in queue_timeout()
71 return !!dc->worker; in delay_is_fast()
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/linux/Documentation/i2c/
H A Dslave-testunit-backend.rst1 .. SPDX-License-Identifier: GPL-2.0
7 by Wolfram Sang <wsa@sang-engineering.com> in 2020
11 easy to obtain). Examples include multi-master testing, and SMBus Host Notify
21 # echo "slave-testunit 0x1030" > /sys/bus/i2c/devices/i2c-0/new_device
30 compatible = "slave-testunit";
39 When writing, the device consists of 4 8-bit registers and, except for some
43 .. csv-table::
49 0x03, DELAY, delay in n * 10ms until test is started
51 Using 'i2cset' from the i2c-tools package, the generic command looks like::
53 # i2cset -y <bus_num> <testunit_address> <CMD> <DATAL> <DATAH> <DELAY> i
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/linux/drivers/iio/imu/
H A Dadis.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/delay.h>
27 * __adis_write_reg() - write N bytes to register (unlocked version)
41 .tx_buf = adis->tx, in __adis_write_reg()
44 .delay.value = adis->data->write_delay, in __adis_write_reg()
45 .delay.unit = SPI_DELAY_UNIT_USECS, in __adis_write_reg()
47 .tx_buf = adis->tx + 2, in __adis_write_reg()
50 .delay.value = adis->data->write_delay, in __adis_write_reg()
51 .delay.unit = SPI_DELAY_UNIT_USECS, in __adis_write_reg()
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/linux/Documentation/devicetree/bindings/mmc/
H A Dsprd,sdhci-r11.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
16 const: sprd,sdhci-r11
27 - description: SDIO source clock
28 - description: gate clock for enabling/disabling the device
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/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr3-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr3-timings
19 Maximum DDR clock frequency for the speed-bin, in Hz.
20 Property is deprecated, use max-freq.
23 max-freq:
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H A Djedec,lpddr3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - samsung,K3QF2F20DB
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/linux/drivers/net/wireless/ath/ath9k/
H A Drng.c27 u32 v1, v2, rng_last = sc->rng_last; in ath9k_rng_data_read()
28 struct ath_hw *ah = sc->sc_ah; in ath9k_rng_data_read()
50 sc->rng_last = rng_last; in ath9k_rng_data_read()
57 u32 delay; in ath9k_rng_delay_get() local
60 delay = 10; in ath9k_rng_delay_get()
62 delay = 1000; in ath9k_rng_delay_get()
64 delay = 10000; in ath9k_rng_delay_get()
66 return delay; in ath9k_rng_delay_get()
91 bytes_read = -EIO; in ath9k_rng_read()
98 struct ath_hw *ah = sc->sc_ah; in ath9k_rng_start()
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/linux/tools/testing/selftests/thermal/intel/workload_hint/
H A Dworkload_hint_test.c1 // SPDX-License-Identifier: GPL-2.0
55 int delay = 0; in main() local
57 printf("Usage: workload_hint_test [notification delay in milli seconds]\n"); in main()
60 ret = sscanf(argv[1], "%d", &delay); in main()
62 printf("Invalid delay\n"); in main()
66 printf("Setting notification delay to %d ms\n", delay); in main()
67 if (delay < in main()
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/linux/Documentation/devicetree/bindings/spi/
H A Dcdns,qspi-nor-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for the Cadence QSPI controller.
10 See spi-peripheral-props.yaml for more info.
13 - Vaishnav Achath <vaishnav.a@ti.com>
16 # cdns,qspi-nor.yaml
17 cdns,read-delay:
20 Delay for read capture logic, in clock cycles.
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H A Dspi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cs-high, etc. or they could
12 be controller specific like delay in clock or data lines, etc. These
14 per-peripheral and there can be multiple peripherals attached to a
20 - Mark Brown <broonie@kernel.org>
28 - minimum: 0
[all …]
/linux/include/linux/reset/
H A Dreset-simple.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 * Maxime Ripard <maxime.ripard@free-electrons.com>
16 #include <linux/reset-controller.h>
20 * struct reset_simple_data - driver data for simple reset controllers
21 * @lock: spinlock to protect registers during read-modify-write cycles
27 * @status_active_low: if true, bits read back as cleared while the reset is
28 * asserted. Otherwise, bits read back as set while the
30 * @reset_us: Minimum delay in microseconds needed that needs to be
32 * device. If multiple consumers with different delay
34 * be the largest minimum delay. 0 means that such a delay is
/linux/Documentation/hwmon/
H A Dnsa320.rst22 Adam Baker <linux@baker-net.org.uk>
25 -----------
35 that contains 0x55 as a marker to indicate that data is being read correctly,
40 sysfs-Interface
41 ---------------
49 -----
52 provided kernel. Testing has shown that if the delay between chip select and
56 read twice corrupting the output. The above analysis is based upon a sample
57 of one unit but suggests that the Zyxel provided delay values include a
62 time to read the data from the device and when it does it reads both temp and
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/linux/include/uapi/linux/
H A Dtaskstats.h1 /* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */
2 /* taskstats.h - exporting per-task statistics
22 /* Format for per-task data returned to userland when
23 * - a task exits
24 * - listener requests stats for a task
33 * c) add new fields after version comment; maintain 64-bit alignment
57 /* Delay accounting fields start
59 * All values, until comment "Delay accounting fields end" are
60 * available only if delay accounting is enabled, even though the last
63 * xxx_count is the number of delay values recorded
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/linux/include/linux/platform_data/
H A Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
36 u32 cs_rd_off; /* Read deassertion time */
41 u32 adv_rd_off; /* Read deassertion time */
44 u32 adv_aad_mux_rd_off; /* ADV read deassertion time for AAD */
58 u32 page_burst_access; /* Multiple access word delay */
59 u32 access; /* Start-cycle to first data valid delay */
60 u32 rd_cycle; /* Total read cycle time */
95 u32 t_rd_cycle; /* read cycle time */
[all …]
/linux/arch/arm/boot/dts/gemini/
H A Dgemini-dlink-dns-313.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for D-Link DNS-313 1-Bay Network Storage Enclosure
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/thermal/thermal.h>
13 model = "D-Link DNS-313 1-Bay Network Storage Enclosure";
14 compatible = "dlink,dns-313", "cortina,gemini";
15 #address-cells = <1>;
16 #size-cells = <1>;
19 /* 64 MB SDRAM in a Nanya NT5DS32M16BS-6K package */
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/linux/drivers/scsi/qla4xxx/
H A Dql4_83xx.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2003-2013 QLogic Corporation
17 return readl((void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_rd_reg()
22 writel(val, (void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_wr_reg()
30 qla4_83xx_wr_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num), addr); in qla4_83xx_set_win_base()
31 val = qla4_83xx_rd_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num)); in qla4_83xx_set_win_base()
33 ql4_printk(KERN_ERR, ha, "%s: Failed to set register window : addr written 0x%x, read 0x%x!\n", in qla4_83xx_set_win_base()
52 ql4_printk(KERN_ERR, ha, "%s: failed read of addr 0x%x!\n", in qla4_83xx_rd_reg_indirect()
91 __func__, ha->func_num, lock_owner); in qla4_83xx_flash_lock()
98 qla4_83xx_wr_reg(ha, QLA83XX_FLASH_LOCK_ID, ha->func_num); in qla4_83xx_flash_lock()
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/linux/arch/mips/sgi-ip22/
H A Dip22-nvram.c1 // SPDX-License-Identifier: GPL-2.0
3 * ip22-nvram.c: NVRAM and serial EEPROM handling.
5 * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
13 #define EEPROM_READ 0xc000 /* serial memory read */
18 #define EEPROM_PRREAD 0xc000 /* read protect register */
31 #define delay() ({ \ macro
39 delay(); \
61 ser_cmd = cmd | (reg << (16 - BITS_IN_COMMAND)); in eeprom_cmd()
68 delay(); in eeprom_cmd()
70 delay(); in eeprom_cmd()
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/linux/samples/bpf/
H A Dibumad_user.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
41 printf("failed to read key %u\n", key); in dump_counts()
51 printf("Read 'Class : count'\n"); in dump_all_counts()
62 bpf_link__destroy(tp_links[--tp_cnt]); in dump_exit()
70 {"delay", required_argument, NULL, 'd'},
77 " --help, -h this menu\n" in usage()
78 " --delay, -d <delay> wait <delay> sec between prints [1 - 1000000]\n" in usage()
86 unsigned long delay = 5; in main() local
89 int opt, err = -1; in main()
92 long_options, &longindex)) != -1) { in main()
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