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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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H A Darm,pl172.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl172.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
18 - arm,pl172
19 - arm,pl175
20 - arm,pl176
22 - compatible
27 - enum:
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H A Dst,stm32-fmc2-ebi-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
25 8: Synchronous read synchronous write PSRAM.
26 9: Synchronous read asynchronous write PSRAM.
27 10: Synchronous read synchronous write NOR.
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H A Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
6 can be accessed at any given time via four chip selects with 64M byte access
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
[all …]
/linux/include/linux/platform_data/
H A Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
36 u32 cs_rd_off; /* Read deassertion time */
41 u32 adv_rd_off; /* Read deassertion time */
44 u32 adv_aad_mux_rd_off; /* ADV read deassertion time for AAD */
57 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
58 u32 page_burst_access; /* Multiple access word delay */
59 u32 access; /* Start-cycle to first data valid delay */ member
60 u32 rd_cycle; /* Total read cycle time */
[all …]
/linux/include/soc/at91/
H A Dat91sam9_ddrsdr.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
48 #define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Onl…
51 #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
52 #define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
53 #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
54 #define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
55 #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
57 #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
58 #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
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/linux/Documentation/i2c/
H A Dslave-testunit-backend.rst1 .. SPDX-License-Identifier: GPL-2.0
7 by Wolfram Sang <wsa@sang-engineering.com> in 2020
11 easy to obtain). Examples include multi-master testing, and SMBus Host Notify
21 # echo "slave-testunit 0x1030" > /sys/bus/i2c/devices/i2c-0/new_device
30 compatible = "slave-testunit";
39 When writing, the device consists of 4 8-bit registers and, except for some
43 .. csv-table::
49 0x03, DELAY, delay in n * 10ms until test is started
51 Using 'i2cset' from the i2c-tools package, the generic command looks like::
53 # i2cset -y <bus_num> <testunit_address> <CMD> <DATAL> <DATAH> <DELAY> i
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/linux/Documentation/ABI/testing/
H A Dsysfs-class-power-gaokun1 What: /sys/class/power_supply/gaokun-ec-battery/smart_charge_delay
6 This entry allows configuration of smart charging delay.
9 for delay hours, battery charging will follow the rules of
12 sysfs-class-power.
14 Access: Read, Write
16 Valid values: In hours (non-negative)
18 What: /sys/class/power_supply/gaokun-ec-battery/battery_adaptive_charge
25 Access: Read, Write
/linux/lib/
H A DKconfig.kcsan1 # SPDX-License-Identifier: GPL-2.0-only
7 def_bool (CC_IS_CLANG && $(cc-option,-fsanitize=thread -mllvm -tsan-distinguish-volatil
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/linux/Documentation/devicetree/bindings/spi/
H A Dst,stm32mp25-ospi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/st,stm32mp25-ospi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
13 - $ref: spi-controller.yaml#
17 const: st,stm32mp25-ospi
22 memory-region:
24 Memory region to be used for memory-map read access.
25 In memory-mapped mode, read access are performed from the memory
[all …]
/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
12 /* [15:0] The Version register for H264 core (Read Only) */
23 /* Enable bit for Host Burst Access */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
138 * If DSP_MB_WAIT == 0, MB delay is DSP_MB_DELAY * 16
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr2-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr2-timings
16 max-freq:
19 Maximum DDR clock frequency for the speed-bin, in Hz.
21 min-freq:
[all …]
H A Djedec,lpddr3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - samsung,K3QF2F20DB
[all …]
/linux/Documentation/hwmon/
H A Dnsa320.rst22 Adam Baker <linux@baker-net.org.uk>
25 -----------
35 that contains 0x55 as a marker to indicate that data is being read correctly,
40 sysfs-Interface
41 ---------------
49 -----
51 The access timings used in the driver are the same as used in the Zyxel
52 provided kernel. Testing has shown that if the delay between chip select and
56 read twice corrupting the output. The above analysis is based upon a sample
57 of one unit but suggests that the Zyxel provided delay values include a
[all …]
/linux/drivers/platform/chrome/
H A Dcros_ec_lpc_mec.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/delay.h>
22 * access memmap data. When set, this mutex is used in preference to
30 * cros_ec_lpc_mec_lock() - Acquire mutex for EMI
46 return -EBUSY; in cros_ec_lpc_mec_lock()
52 * cros_ec_lpc_mec_unlock() - Release mutex for EMI
67 return -EBUSY; in cros_ec_lpc_mec_unlock()
73 * cros_ec_lpc_mec_emi_write_address() - Initialize EMI at a given address.
75 * @addr: Starting read / write address
76 * @access_type: Type of access, typically 32-bit auto-increment
[all …]
/linux/drivers/spi/
H A Dspi-rspi.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on spi-sh.c:
21 #include <linux/dma-mapping.h>
38 #define RSPI_SPCKD 0x0c /* Clock Delay Register */
39 #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
40 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
68 /* SPCR - Control Register */
77 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
78 /* QSPI on R-Car Gen2 only */
79 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
[all …]
/linux/Documentation/driver-api/
H A Dntb.rst5 NTB (Non-Transparent Bridge) is a type of PCI-Express bridge chip that connects
6 the separate memory systems of two or more computers to the same PCI-Express
9 scratchpad and message registers. Scratchpad registers are read-and-writable
15 Memory windows allow translated read and write access to the peer memory.
36 ----------------------------------------
50 | dma-mapped |-ntb_mw_set_trans(addr) |
52 | (addr) |<======| MW xlat addr |<====| MW base addr |<== memory-mapped IO
53 |------------| |--------------| | |--------------|
58 maps corresponding outbound memory window so to have access to the shared
68 | dma-mapped | | | MW base addr |<== memory-mapped IO
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/linux/kernel/kcsan/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/delay.h>
54 /* Per-CPU kcsan_ctx for interrupts */
63 * The purpose is 2-fold:
71 * given this should be rare, this is a reasonable trade-off to make, since this
87 * SLOT_IDX_FAST is used in the fast-path. Not first checking the address's primary
96 * able to safely update and access a watchpoint without introducing locking
98 * zero-initialized state matches INVALID_WATCHPOINT.
100 * Add NUM_SLOTS-1 entries to account for overflow; this helps avoid having to
101 * use more complicated SLOT_IDX_FAST calculation with modulo in the fast-path.
[all …]
/linux/drivers/memory/
H A Dpl172.c1 // SPDX-License-Identifier: GPL-2.0
9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
69 dev_err(&adev->dev, "%s timing too tight\n", name); in pl172_timing_prop()
70 return -EINVAL; in pl172_timing_prop()
73 writel(cycles, pl172->base + reg_offset); in pl172_timing_prop()
76 dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start + in pl172_timing_prop()
77 readl(pl172->base + reg_offset)); in pl172_timing_prop()
90 if (!of_property_read_u32(np, "mpmc,memory-width", &cfg)) { in pl172_setup_static()
98 dev_err(&adev->dev, "invalid memory width cs%u\n", cs); in pl172_setup_static()
[all …]
/linux/drivers/misc/c2port/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <linux/delay.h>
63 struct c2port_ops *ops = dev->ops; in c2port_reset()
69 ops->c2ck_set(dev, 0); in c2port_reset()
71 ops->c2ck_set(dev, 1); in c2port_reset()
79 struct c2port_ops *ops = dev->ops; in c2port_strobe_ck()
81 /* During hi-low-hi transition we disable local IRQs to avoid in c2port_strobe_ck()
87 ops->c2ck_set(dev, 0); in c2port_strobe_ck()
89 ops->c2ck_set(dev, 1); in c2port_strobe_ck()
101 struct c2port_ops *ops = dev->ops; in c2port_write_ar()
[all …]
/linux/drivers/hwmon/pmbus/
H A Ducd9000.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/delay.h>
79 * It has been observed that the UCD90320 randomly fails register access when
80 * doing another access right on the back of a register write. To mitigate this
81 * make sure that there is a minimum delay between a write access and the
82 * following access. The 500 is based on experimental data. At a delay of
94 if (data->fan_data[fan][3] & 1) in ucd9000_get_fan_config()
98 fan_config |= (data->fan_data[fan][3] & 0x06) >> 1; in ucd9000_get_fan_config()
111 return -ENXIO; in ucd9000_read_byte_data()
125 return -ENXIO; in ucd9000_read_byte_data()
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap2420-n8x0-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 stdout-path = &uart3;
16 compatible = "i2c-cbus-gpio";
21 #address-cells = <1>;
22 #size-cells = <0>;
25 interrupt-parent = <&gpio4>;
34 clock-frequency = <400000>;
44 clock-frequency = <400000>;
50 /* gpio-irq for dma: 26 */
53 #address-cells = <1>;
[all …]
H A Domap3-gta04a5one.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-18 H. Nikolaus Schaller <hns@goldelico.com>
6 #include "omap3-gta04a5.dts"
13 gpmc_pins: gpmc-pins {
14 pinctrl-single,pins = <
45 pinctrl-names = "default";
46 pinctrl-0 = <&gpmc_pins>;
48 /delete-node/ nand@0,0;
52 #address-cells = <1>;
53 #size-cells = <1>;
[all …]
/linux/drivers/mtd/nand/raw/
H A Dnand_legacy.c1 // SPDX-License-Identifier: GPL-2.0
4 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 #include <linux/delay.h>
23 * nand_read_byte - [DEFAULT] read one byte from the chip
26 * Default read function for 8bit buswidth
30 return readb(chip->legacy.IO_ADDR_R); in nand_read_byte()
34 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
37 * Default read function for 16bit buswidth with endianness conversion.
42 return (uint8_t) cpu_to_le16(readw(chip->legacy.IO_ADDR_R)); in nand_read_byte16()
46 * nand_select_chip - [DEFAULT] control CE line
[all …]
/linux/sound/pci/asihpi/
H A Dhpi6000.c1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 1997-2011 AudioScience Inc. <support@audioscience.com>
18 (C) Copyright AudioScience Inc. 1998-2003
72 /* can't access PCI2040 */
74 /* can't access DSP HPI i/f */
76 /* can't access internal DSP memory */
78 /* can't access SDRAM - test#1 */
80 /* can't access SDRAM - test#2 */
210 switch (phm->function) { in subsys_message()
215 phr->error = HPI_ERROR_INVALID_FUNC; in subsys_message()
[all …]

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