Lines Matching +full:read +full:- +full:access +full:- +full:delay

1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
4  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
34  * Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
65  * Delay n microseconds.
67 #define	OS_DELAY(_n)	DELAY(_n)
79  * The hardware registers are native little-endian byte order.
80  * Big-endian hosts are handled by enabling hardware byte-swap
82  * domain registers are not byte swapped!  Thus, on big-endian
83  * platforms we have to explicitly byte-swap those registers.
99  * For USB/SDIO support (where access latencies are quite high);
101  * either a read is done, or an explicit flush is done.
113  * Read and write barriers.  Some platforms require more strongly ordered
117  * Read barriers should occur before each read, and write barriers
120  * Later on for SDIO/USB parts we will methodize this and make them no-ops;
128 	bus_space_barrier((bus_space_tag_t)(_ah)->ah_st,	\
129 	    (bus_space_handle_t)(_ah)->ah_sh, (_start), (_len), (_t))
134  * Register read/write operations are handled through
135  * platform-dependent routines.