| /linux/include/linux/ |
| H A D | hp_sdc.h | 2 * HP i8042 System Device Controller -- header
10 * 1. Redistributions of source code must retain the above copyright
31 * HP-HIL Technical Reference Manual. Hewlett Packard Product No. 45918A
34 * for Part Number 1820-4784 Revision B. Dwg No. A-1820-4784-2
104 #define HP_SDC_STATUS_PUP 0x70 /* Successful power-up self test */
134 #define HP_SDC_STR 0x7f /* i8042 self-test result */
146 #define HP_SDC_CFG_ROLLOVER 0x08 /* WTF is "N-key rollover"? */
149 #define HP_SDC_CFG_KBD_OLD 0x03 /* keyboard code for non-HIL */
150 #define HP_SDC_CFG_KBD_NEW 0x07 /* keyboard code from HIL autoconfig */
151 #define HP_SDC_CFG_REV 0x40 /* Code revision bit */
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| H A D | crash_dump.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 #define ELFCORE_ADDR_MAX (-1ULL)
13 #define ELFCORE_ADDR_ERR (-2ULL)
36 /* Architecture code defines this if there are other possible ELF
37 * machine types, e.g. on bi-arch capable hardware. */
43 * Architecture code can redefine this if there are any special checks
44 * needed for 32-bit ELF or 64-bi
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| /linux/Documentation/arch/arm/ |
| H A D | porting.rst | 5 Taken from list archive at http://lists.arm.linux.org.uk/pipermail/linux-arm-kernel/2001-July/00406…
8 -------------------
14 phys = virt - PAGE_OFFSET + PHYS_OFFSET
18 --------------------
23 the time when you call the decompressor code. You normally call
25 to be located in RAM, it can be in flash or other read-only or
26 read-write addressable medium.
29 Start address of zero-initialised work area for the decompressor.
30 This must be pointing at RAM. The decompressor will zero initialise
43 Physical address to place the initial RAM disk. Only relevant if
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| H A D | tcm.rst | 2 ARM TCM (Tightly-Coupled Memory) handling in Linux
7 Some ARM SoCs have a so-called TCM (Tightly-Coupled Memory).
8 This is usually just a few (4-64) KiB of RAM inside the ARM
12 Harvard-architecture, so there is an ITCM (instruction TCM)
24 determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
32 place you put it, it will mask any underlying RAM from the
33 CPU so it is usually wise not to overlap any physical RAM with
52 - FIQ and other interrupt handlers that need deterministic
55 - Idle loops where all external RAM is set to self-refresh
56 retention mode, so only on-chip RAM is accessible by
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| /linux/drivers/net/ethernet/amd/ |
| H A D | mvme147.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Uses the generic 7990.c LANCE code.
30 /* We have 32K of RAM for the init block and buffers. This places
37 #include "7990.h" /* use generic LANCE code */
42 unsigned long ram; member
47 * plus board-specific init, open and close actions.
48 * Oh, and we need to tell the generic code how to read and write LANCE registers...
70 /* Initialise the one and only on-board 7990 */
83 return ERR_PTR(-ENODEV); in mvme147lance_probe()
88 return ERR_PTR(-ENOMEM); in mvme147lance_probe()
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| /linux/drivers/net/ethernet/intel/i40e/ |
| H A D | i40e_nvm.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
10 * i40e_init_nvm - Initialize NVM function pointers
17 * We are accessing FLASH always thru the Shadow RAM.
21 struct i40e_nvm_info *nvm = &hw->nvm; in i40e_init_nvm()
32 nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB; in i40e_init_nvm()
38 nvm->timeout = I40E_MAX_NVM_TIMEOUT; in i40e_init_nvm()
39 nvm->blank_nvm_mode = false; in i40e_init_nvm()
41 nvm->blank_nvm_mode = true; in i40e_init_nvm()
42 ret_code = -EIO; in i40e_init_nvm()
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| /linux/arch/riscv/include/asm/ |
| H A D | xip_fixup.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
12 /* Fix-up address in Flash into address in RAM early during boot before
13 * MMU is up. Because generated code "thinks" data is in Flash, but it
14 * is actually in RAM (actually data is also in Flash, but Flash is
15 * read-only, thus we need to use the data residing in RAM).
17 * The start of data in Flash is _sdata and the start of data in RAM is
18 * CONFIG_PHYS_RAM_BASE. So this fix-up essentially does this:
19 * reg += CONFIG_PHYS_RAM_BASE - _start
27 /* In linker script, at the transition from read-only section to
32 * Consequently, early during boot before MMU is up, the generated code
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| /linux/arch/arm/kernel/ |
| H A D | tcm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2009 ST-Ericsson AB
41 .name = "DTCM RAM",
48 .name = "ITCM RAM",
114 const int tcm_sizes[16] = { 0, -1, -1, 4, 8, 16, 32, 64, 128, in setup_tcm_bank()
115 256, 512, 1024, -1, -1, -1, -1 }; in setup_tcm_bank()
141 return -EINVAL; in setup_tcm_bank()
145 return -EINVAL; in setup_tcm_bank()
183 * When we are running in the non-secure world and the secure world
200 * In this particular case (MRC with ARM condition code ALways) the
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| H A D | reboot.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
30 * code.
88 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
89 * kexec'd kernel to use any and all RAM as it sees fit, without having to
90 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
111 * Power-off simply requires that the secondary CPUs stop performing any
129 * This is required so that any code running after reset on the primary CPU
130 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
131 * executing pre-reset code, and using RAM that the primary CPU's code wishes
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | nvidia,tegra20-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
17 various performance-affecting settings beyond the obvious SDRAM configuration
23 const: nvidia,tegra20-emc
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| H A D | nvidia,tegra124-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
22 const: nvidia,tegra124-mc
30 clock-names:
32 - const: mc
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| H A D | nvidia,tegra30-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
39 const: nvidia,tegra30-mc
47 clock-names:
49 - const: mc
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| /linux/arch/x86/kernel/ |
| H A D | ebda.c | 1 // SPDX-License-Identifier: GPL-2.0
12 * are code), that must not be used by the kernel as available
13 * RAM.
20 * guess the reserved BIOS area by looking at the low BIOS RAM size
26 * - This code also contains a quirk for Dell systems that neglect
27 * to reserve the EBDA area in the 'RAM size' value ...
29 * - The same quirk also avoids a problem with the AMD768MPX
34 * - Plus paravirt systems don't have a reliable value in the
35 * 'BIOS RAM size' pointer we can rely on, so we must quirk
70 * BIOS RAM size is encoded in kilobytes, convert it in reserve_bios_regions()
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| /linux/drivers/cpuidle/ |
| H A D | cpuidle-zynq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013 Xilinx
7 * based on arch/arm/mach-at91/cpuidle.c
9 * The cpu idle uses wait-for-interrupt and RAM self refresh in order
10 * to implement two idle states -
11 * #1 wait-for-interrupt
12 * #2 wait-for-interrupt and RAM self refresh
24 /* Actual code that puts the SoC in different idle states */
28 /* Add code for DDR self refresh start */ in zynq_enter_idle()
44 .desc = "WFI and RAM Self Refresh",
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| /linux/arch/microblaze/kernel/ |
| H A D | setup.c | 2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2007-2009 PetaLogix
32 #include <linux/dma-mapping.h>
46 * ASM code. Default position is BSS section which is cleared
70 code (ie no point checking for CRAMFS if it's not even enabled) */
74 if (memcmp(&addr[0], "-rom1fs-", 8) == 0) /* romfs */ in get_romfs_len()
88 void __init machine_early_init(const char *cmdline, unsigned int ram, in machine_early_init() argument
104 romfs_base = (ram ? ram : (unsigned int)&__init_end); in machine_early_init()
119 memset(__bss_start, 0, __bss_stop-__bss_start); in machine_early_init()
120 memset(_ssbss, 0, _esbss-_ssbss); in machine_early_init()
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| /linux/Documentation/admin-guide/pm/ |
| H A D | sleep-states.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 Sleep states are global low-power states of the entire system in which user
14 space code cannot be executed and the overall system activity is significantly
28 Suspend-to-Idle
29 ---------------
31 This is a generic, pure software, light-weight variant of system suspend (also
34 I/O devices into low-power states (possibly lower-power than available in the
38 The system is woken up from this state by in-band interrupts, so theoretically
43 or :ref:`suspend-to-RAM <s2ram>`, or it can be used in addition to any of the
50 -------
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| /linux/arch/m68k/atari/ |
| H A D | stram.c | 2 * Functions for ST-RAM allocations
4 * Copyright 1994-97 Roman Hodek <Roman.Hodek@informatik.uni-erlangen.de>
35 * The ST-RAM allocator allocates memory from a pool of reserved ST-RAM of
36 * configurable size, set aside on ST-RAM init.
37 * As long as this pool is not exhausted, allocation of real ST-RAM can be
41 /* set if kernel is in ST-RAM */
45 .name = "ST-RAM Pool"
73 * determine whether kernel code resides in ST-RAM in atari_stram_init()
74 * (then ST-RAM is the first memory block at virtual 0x0) in atari_stram_init()
84 /* Should never come here! (There is always ST-Ram!) */ in atari_stram_init()
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| /linux/arch/m68k/coldfire/ |
| H A D | head.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * head.S -- common startup code for ColdFire CPUs.
7 * (C) Copyright 1999-2011, Greg Ungerer <gerg@snapgear.com>.
14 #include <asm/asm-offsets.h>
23 * If we don't have a fixed memory size, then lets build in code
26 * that do not have their RAM starting at address 0, and it only
40 * but the DCMR register is virtually identical - give or take
119 * During startup we store away the RAM setup. These are not in the
182 movel #CONFIG_RAMBASE,%a7 /* mark the base of RAM */
185 GET_MEM_SIZE /* macro code determines size */
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| /linux/Documentation/scsi/ |
| H A D | ChangeLog.ncr53c8xx | 1 Sat May 12 12:00 2001 Gerard Roudier (groudier@club-internet.fr)
2 * version ncr53c8xx-3.4.3b
3 - Ensure LEDC bit in GPCNTL is cleared when reading the NVRAM.
4 Fix sent by Stig Telfer <stig@api-networks.com>.
5 - Define scsi_set_pci_device() as nil for kernel < 2.4.4.
7 Mon Feb 12 22:30 2001 Gerard Roudier (groudier@club-internet.fr)
8 * version ncr53c8xx-3.4.3
9 - Call pci_enable_device() as AC wants this to be done.
10 - Get both the BAR cookies actual and PCI BAR values.
12 - Merge changes for linux-2.4 that declare the host template
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| /linux/arch/nios2/kernel/ |
| H A D | head.S | 23 #include <asm/asm-offsets.h>
24 #include <asm/asm-macros.h>
27 * ZERO_PAGE is a special page that is used for zero-initialized
48 * Input(s): passed from u-boot
49 * r4 - Optional pointer to a board information structure.
50 * r5 - Optional pointer to the physical starting address of the init RAM
52 * r6 - Optional pointer to the physical ending address of the init RAM
54 * r7 - Optional pointer to the physical starting address of any kernel
55 * command-line parameters.
59 * First executable code - detected and jumped to by the ROM bootstrap
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| /linux/Documentation/admin-guide/ |
| H A D | ramoops.rst | 9 ------------
11 Ramoops is an oops/panic logger that writes its logs to RAM before the system
13 needs a system with persistent RAM so that the content of that area can
17 ----------------
56 to life (i.e. a watchdog triggered). In such cases, RAM may be somewhat
60 ----------------------
68 the kernel to use only the first 128 MB of memory, and place ECC-protected
74 ``Documentation/devicetree/bindings/reserved-memory/ramoops.yaml``.
77 reserved-memory {
78 #address-cells = <2>;
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| /linux/drivers/memory/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
42 Used to configure the EBI (external bus interface) when the device-
53 provide current information about the system's RAM, for instance
55 for the DRAM's temperature. Slower refresh rate means cooler RAM,
56 higher refresh rate means hotter RAM.
68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
75 tags and way-select latencies of RAM access. This driver provides a
76 dt properties-based and sysfs interface for it.
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| /linux/Documentation/devicetree/bindings/misc/ |
| H A D | nvidia,tegra20-apbmisc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/nvidia,tegra20-apbmisc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - items:
17 - enum:
18 - nvidia,tegra210-apbmisc
19 - nvidia,tegra124-apbmisc
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| /linux/arch/arm/boot/dts/marvell/ |
| H A D | kirkwood-ts219-6281.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "kirkwood-6281.dtsi"
6 #include "kirkwood-ts219.dtsi"
10 pinctrl: pin-controller@10000 {
12 pinctrl-0 = <&pmx_ram_size &pmx_board_id>;
13 pinctrl-names = "default";
15 pmx_ram_size: pmx-ram-size {
16 /* RAM: 0: 256 MB, 1: 512 MB */
20 pmx_USB_copy_button: pmx-USB-copy-button {
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| H A D | kirkwood-ts219-6282.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "kirkwood-6282.dtsi"
6 #include "kirkwood-ts219.dtsi"
10 pinctrl: pin-controller@10000 {
12 pinctrl-0 = <&pmx_ram_size &pmx_board_id>;
13 pinctrl-names = "default";
15 pmx_ram_size: pmx-ram-size {
16 /* RAM: 0: 256 MB, 1: 512 MB */
20 pmx_reset_button: pmx-reset-button {
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