1af873fceSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2bc581770SLinus Walleij /*
3bc581770SLinus Walleij * Copyright (C) 2008-2009 ST-Ericsson AB
4bc581770SLinus Walleij * TCM memory handling for ARM systems
5bc581770SLinus Walleij *
6bc581770SLinus Walleij * Author: Linus Walleij <linus.walleij@stericsson.com>
7bc581770SLinus Walleij * Author: Rickard Andersson <rickard.andersson@stericsson.com>
8bc581770SLinus Walleij */
9bc581770SLinus Walleij #include <linux/init.h>
10bc581770SLinus Walleij #include <linux/kernel.h>
11bc581770SLinus Walleij #include <linux/module.h>
12bc581770SLinus Walleij #include <linux/stddef.h>
13bc581770SLinus Walleij #include <linux/ioport.h>
14bc581770SLinus Walleij #include <linux/genalloc.h>
15bc581770SLinus Walleij #include <linux/string.h> /* memcpy */
16bc581770SLinus Walleij #include <asm/cputype.h>
17bc581770SLinus Walleij #include <asm/mach/map.h>
18*a9ff6961SLinus Walleij #include <asm/page.h>
199f97da78SDavid Howells #include <asm/system_info.h>
200bbe6b5aSMichael van der Westhuizen #include <asm/traps.h>
215b1e58c7SBen Dooks #include <asm/tcm.h>
220bbe6b5aSMichael van der Westhuizen
230bbe6b5aSMichael van der Westhuizen #define TCMTR_FORMAT_MASK 0xe0000000U
24bc581770SLinus Walleij
25bc581770SLinus Walleij static struct gen_pool *tcm_pool;
26201043f2SLinus Walleij static bool dtcm_present;
27201043f2SLinus Walleij static bool itcm_present;
28bc581770SLinus Walleij
29bc581770SLinus Walleij /* TCM section definitions from the linker */
30bc581770SLinus Walleij extern char __itcm_start, __sitcm_text, __eitcm_text;
31bc581770SLinus Walleij extern char __dtcm_start, __sdtcm_data, __edtcm_data;
32bc581770SLinus Walleij
331dbd30e9SLinus Walleij /* These will be increased as we run */
34ca045579SBen Dooks static u32 dtcm_end = DTCM_OFFSET;
35ca045579SBen Dooks static u32 itcm_end = ITCM_OFFSET;
361dbd30e9SLinus Walleij
37bc581770SLinus Walleij /*
38bc581770SLinus Walleij * TCM memory resources
39bc581770SLinus Walleij */
40bc581770SLinus Walleij static struct resource dtcm_res = {
41bc581770SLinus Walleij .name = "DTCM RAM",
42bc581770SLinus Walleij .start = DTCM_OFFSET,
431dbd30e9SLinus Walleij .end = DTCM_OFFSET,
44bc581770SLinus Walleij .flags = IORESOURCE_MEM
45bc581770SLinus Walleij };
46bc581770SLinus Walleij
47bc581770SLinus Walleij static struct resource itcm_res = {
48bc581770SLinus Walleij .name = "ITCM RAM",
49bc581770SLinus Walleij .start = ITCM_OFFSET,
501dbd30e9SLinus Walleij .end = ITCM_OFFSET,
51bc581770SLinus Walleij .flags = IORESOURCE_MEM
52bc581770SLinus Walleij };
53bc581770SLinus Walleij
54bc581770SLinus Walleij static struct map_desc dtcm_iomap[] __initdata = {
55bc581770SLinus Walleij {
56bc581770SLinus Walleij .virtual = DTCM_OFFSET,
57bc581770SLinus Walleij .pfn = __phys_to_pfn(DTCM_OFFSET),
581dbd30e9SLinus Walleij .length = 0,
592e2c9de2SRussell King .type = MT_MEMORY_RW_DTCM
60bc581770SLinus Walleij }
61bc581770SLinus Walleij };
62bc581770SLinus Walleij
63bc581770SLinus Walleij static struct map_desc itcm_iomap[] __initdata = {
64bc581770SLinus Walleij {
65bc581770SLinus Walleij .virtual = ITCM_OFFSET,
66bc581770SLinus Walleij .pfn = __phys_to_pfn(ITCM_OFFSET),
671dbd30e9SLinus Walleij .length = 0,
682e2c9de2SRussell King .type = MT_MEMORY_RWX_ITCM,
69bc581770SLinus Walleij }
70bc581770SLinus Walleij };
71bc581770SLinus Walleij
72bc581770SLinus Walleij /*
73bc581770SLinus Walleij * Allocate a chunk of TCM memory
74bc581770SLinus Walleij */
tcm_alloc(size_t len)75bc581770SLinus Walleij void *tcm_alloc(size_t len)
76bc581770SLinus Walleij {
77bc581770SLinus Walleij unsigned long vaddr;
78bc581770SLinus Walleij
79bc581770SLinus Walleij if (!tcm_pool)
80bc581770SLinus Walleij return NULL;
81bc581770SLinus Walleij
82bc581770SLinus Walleij vaddr = gen_pool_alloc(tcm_pool, len);
83bc581770SLinus Walleij if (!vaddr)
84bc581770SLinus Walleij return NULL;
85bc581770SLinus Walleij
86bc581770SLinus Walleij return (void *) vaddr;
87bc581770SLinus Walleij }
88bc581770SLinus Walleij EXPORT_SYMBOL(tcm_alloc);
89bc581770SLinus Walleij
90bc581770SLinus Walleij /*
91bc581770SLinus Walleij * Free a chunk of TCM memory
92bc581770SLinus Walleij */
tcm_free(void * addr,size_t len)93bc581770SLinus Walleij void tcm_free(void *addr, size_t len)
94bc581770SLinus Walleij {
95bc581770SLinus Walleij gen_pool_free(tcm_pool, (unsigned long) addr, len);
96bc581770SLinus Walleij }
97bc581770SLinus Walleij EXPORT_SYMBOL(tcm_free);
98bc581770SLinus Walleij
tcm_dtcm_present(void)99201043f2SLinus Walleij bool tcm_dtcm_present(void)
100201043f2SLinus Walleij {
101201043f2SLinus Walleij return dtcm_present;
102201043f2SLinus Walleij }
103201043f2SLinus Walleij EXPORT_SYMBOL(tcm_dtcm_present);
104201043f2SLinus Walleij
tcm_itcm_present(void)105201043f2SLinus Walleij bool tcm_itcm_present(void)
106201043f2SLinus Walleij {
107201043f2SLinus Walleij return itcm_present;
108201043f2SLinus Walleij }
109201043f2SLinus Walleij EXPORT_SYMBOL(tcm_itcm_present);
110201043f2SLinus Walleij
setup_tcm_bank(u8 type,u8 bank,u8 banks,u32 * offset)1111dbd30e9SLinus Walleij static int __init setup_tcm_bank(u8 type, u8 bank, u8 banks,
1121dbd30e9SLinus Walleij u32 *offset)
113bc581770SLinus Walleij {
114bc581770SLinus Walleij const int tcm_sizes[16] = { 0, -1, -1, 4, 8, 16, 32, 64, 128,
115bc581770SLinus Walleij 256, 512, 1024, -1, -1, -1, -1 };
116bc581770SLinus Walleij u32 tcm_region;
117bc581770SLinus Walleij int tcm_size;
118bc581770SLinus Walleij
11959850977SLinus Walleij /*
12059850977SLinus Walleij * If there are more than one TCM bank of this type,
12159850977SLinus Walleij * select the TCM bank to operate on in the TCM selection
12259850977SLinus Walleij * register.
12359850977SLinus Walleij */
12459850977SLinus Walleij if (banks > 1)
12559850977SLinus Walleij asm("mcr p15, 0, %0, c9, c2, 0"
12659850977SLinus Walleij : /* No output operands */
12759850977SLinus Walleij : "r" (bank));
12859850977SLinus Walleij
129bc581770SLinus Walleij /* Read the special TCM region register c9, 0 */
130bc581770SLinus Walleij if (!type)
131bc581770SLinus Walleij asm("mrc p15, 0, %0, c9, c1, 0"
132bc581770SLinus Walleij : "=r" (tcm_region));
133bc581770SLinus Walleij else
134bc581770SLinus Walleij asm("mrc p15, 0, %0, c9, c1, 1"
135bc581770SLinus Walleij : "=r" (tcm_region));
136bc581770SLinus Walleij
137bc581770SLinus Walleij tcm_size = tcm_sizes[(tcm_region >> 2) & 0x0f];
138bc581770SLinus Walleij if (tcm_size < 0) {
1391dbd30e9SLinus Walleij pr_err("CPU: %sTCM%d of unknown size\n",
14059850977SLinus Walleij type ? "I" : "D", bank);
1411dbd30e9SLinus Walleij return -EINVAL;
1421dbd30e9SLinus Walleij } else if (tcm_size > 32) {
1431dbd30e9SLinus Walleij pr_err("CPU: %sTCM%d larger than 32k found\n",
1441dbd30e9SLinus Walleij type ? "I" : "D", bank);
1451dbd30e9SLinus Walleij return -EINVAL;
146bc581770SLinus Walleij } else {
14759850977SLinus Walleij pr_info("CPU: found %sTCM%d %dk @ %08x, %senabled\n",
148bc581770SLinus Walleij type ? "I" : "D",
14959850977SLinus Walleij bank,
150bc581770SLinus Walleij tcm_size,
151bc581770SLinus Walleij (tcm_region & 0xfffff000U),
152bc581770SLinus Walleij (tcm_region & 1) ? "" : "not ");
153bc581770SLinus Walleij }
154bc581770SLinus Walleij
1559715efb8SLinus Walleij /* Not much fun you can do with a size 0 bank */
1569715efb8SLinus Walleij if (tcm_size == 0)
1579715efb8SLinus Walleij return 0;
1589715efb8SLinus Walleij
159bc581770SLinus Walleij /* Force move the TCM bank to where we want it, enable */
1601dbd30e9SLinus Walleij tcm_region = *offset | (tcm_region & 0x00000ffeU) | 1;
161bc581770SLinus Walleij
162bc581770SLinus Walleij if (!type)
163bc581770SLinus Walleij asm("mcr p15, 0, %0, c9, c1, 0"
164bc581770SLinus Walleij : /* No output operands */
165bc581770SLinus Walleij : "r" (tcm_region));
166bc581770SLinus Walleij else
167bc581770SLinus Walleij asm("mcr p15, 0, %0, c9, c1, 1"
168bc581770SLinus Walleij : /* No output operands */
169bc581770SLinus Walleij : "r" (tcm_region));
170bc581770SLinus Walleij
1711dbd30e9SLinus Walleij /* Increase offset */
1721dbd30e9SLinus Walleij *offset += (tcm_size << 10);
1731dbd30e9SLinus Walleij
17459850977SLinus Walleij pr_info("CPU: moved %sTCM%d %dk to %08x, enabled\n",
175bc581770SLinus Walleij type ? "I" : "D",
17659850977SLinus Walleij bank,
177bc581770SLinus Walleij tcm_size,
178bc581770SLinus Walleij (tcm_region & 0xfffff000U));
1791dbd30e9SLinus Walleij return 0;
180bc581770SLinus Walleij }
181bc581770SLinus Walleij
182bc581770SLinus Walleij /*
1830bbe6b5aSMichael van der Westhuizen * When we are running in the non-secure world and the secure world
1840bbe6b5aSMichael van der Westhuizen * has not explicitly given us access to the TCM we will get an
1850bbe6b5aSMichael van der Westhuizen * undefined error when reading the TCM region register in the
1860bbe6b5aSMichael van der Westhuizen * setup_tcm_bank function (above).
1870bbe6b5aSMichael van der Westhuizen *
1880bbe6b5aSMichael van der Westhuizen * There are two variants of this register read that we need to trap,
1890bbe6b5aSMichael van der Westhuizen * the read for the data TCM and the read for the instruction TCM:
1900bbe6b5aSMichael van der Westhuizen * c0370628: ee196f11 mrc 15, 0, r6, cr9, cr1, {0}
1910bbe6b5aSMichael van der Westhuizen * c0370674: ee196f31 mrc 15, 0, r6, cr9, cr1, {1}
1920bbe6b5aSMichael van der Westhuizen *
1930bbe6b5aSMichael van der Westhuizen * Our undef hook mask explicitly matches all fields of the encoded
1940bbe6b5aSMichael van der Westhuizen * instruction other than the destination register. The mask also
1950bbe6b5aSMichael van der Westhuizen * only allows operand 2 to have the values 0 or 1.
1960bbe6b5aSMichael van der Westhuizen *
1970bbe6b5aSMichael van der Westhuizen * The undefined hook is defined as __init and __initdata, and therefore
1980bbe6b5aSMichael van der Westhuizen * must be removed before tcm_init returns.
1990bbe6b5aSMichael van der Westhuizen *
2000bbe6b5aSMichael van der Westhuizen * In this particular case (MRC with ARM condition code ALways) the
2010bbe6b5aSMichael van der Westhuizen * Thumb-2 and ARM instruction encoding are identical, so this hook
2020bbe6b5aSMichael van der Westhuizen * will work on a Thumb-2 kernel.
2030bbe6b5aSMichael van der Westhuizen *
2040bbe6b5aSMichael van der Westhuizen * See A8.8.107, DDI0406C_C ARM Architecture Reference Manual, Encoding
2050bbe6b5aSMichael van der Westhuizen * T1/A1 for the bit-by-bit details.
2060bbe6b5aSMichael van der Westhuizen *
2070bbe6b5aSMichael van der Westhuizen * mrc p15, 0, XX, c9, c1, 0
2080bbe6b5aSMichael van der Westhuizen * mrc p15, 0, XX, c9, c1, 1
2090bbe6b5aSMichael van der Westhuizen * | | | | | | | +---- opc2 0|1 = 000|001
2100bbe6b5aSMichael van der Westhuizen * | | | | | | +------- CRm 0 = 0001
2110bbe6b5aSMichael van der Westhuizen * | | | | | +----------- CRn 0 = 1001
2120bbe6b5aSMichael van der Westhuizen * | | | | +--------------- Rt ? = ????
2130bbe6b5aSMichael van der Westhuizen * | | | +------------------- opc1 0 = 000
2140bbe6b5aSMichael van der Westhuizen * | | +----------------------- coproc 15 = 1111
2150bbe6b5aSMichael van der Westhuizen * | +-------------------------- condition ALways = 1110
2160bbe6b5aSMichael van der Westhuizen * +----------------------------- instruction MRC = 1110
2170bbe6b5aSMichael van der Westhuizen *
2180bbe6b5aSMichael van der Westhuizen * Encoding this as per A8.8.107 of DDI0406C, Encoding T1/A1, yields:
2190bbe6b5aSMichael van der Westhuizen * 1111 1111 1111 1111 0000 1111 1101 1111 Required Mask
2200bbe6b5aSMichael van der Westhuizen * 1110 1110 0001 1001 ???? 1111 0001 0001 mrc p15, 0, XX, c9, c1, 0
2210bbe6b5aSMichael van der Westhuizen * 1110 1110 0001 1001 ???? 1111 0011 0001 mrc p15, 0, XX, c9, c1, 1
2220bbe6b5aSMichael van der Westhuizen * [ ] [ ] [ ]| [ ] [ ] [ ] [ ]| +--- CRm
2230bbe6b5aSMichael van der Westhuizen * | | | | | | | | +----- SBO
2240bbe6b5aSMichael van der Westhuizen * | | | | | | | +------- opc2
2250bbe6b5aSMichael van der Westhuizen * | | | | | | +----------- coproc
2260bbe6b5aSMichael van der Westhuizen * | | | | | +---------------- Rt
2270bbe6b5aSMichael van der Westhuizen * | | | | +--------------------- CRn
2280bbe6b5aSMichael van der Westhuizen * | | | +------------------------- SBO
2290bbe6b5aSMichael van der Westhuizen * | | +--------------------------- opc1
2300bbe6b5aSMichael van der Westhuizen * | +------------------------------- instruction
2310bbe6b5aSMichael van der Westhuizen * +------------------------------------ condition
2320bbe6b5aSMichael van der Westhuizen */
2330bbe6b5aSMichael van der Westhuizen #define TCM_REGION_READ_MASK 0xffff0fdf
2340bbe6b5aSMichael van der Westhuizen #define TCM_REGION_READ_INSTR 0xee190f11
2350bbe6b5aSMichael van der Westhuizen #define DEST_REG_SHIFT 12
2360bbe6b5aSMichael van der Westhuizen #define DEST_REG_MASK 0xf
2370bbe6b5aSMichael van der Westhuizen
tcm_handler(struct pt_regs * regs,unsigned int instr)2380bbe6b5aSMichael van der Westhuizen static int __init tcm_handler(struct pt_regs *regs, unsigned int instr)
2390bbe6b5aSMichael van der Westhuizen {
2400bbe6b5aSMichael van der Westhuizen regs->uregs[(instr >> DEST_REG_SHIFT) & DEST_REG_MASK] = 0;
2410bbe6b5aSMichael van der Westhuizen regs->ARM_pc += 4;
2420bbe6b5aSMichael van der Westhuizen return 0;
2430bbe6b5aSMichael van der Westhuizen }
2440bbe6b5aSMichael van der Westhuizen
2450bbe6b5aSMichael van der Westhuizen static struct undef_hook tcm_hook __initdata = {
2460bbe6b5aSMichael van der Westhuizen .instr_mask = TCM_REGION_READ_MASK,
2470bbe6b5aSMichael van der Westhuizen .instr_val = TCM_REGION_READ_INSTR,
2480bbe6b5aSMichael van der Westhuizen .cpsr_mask = MODE_MASK,
2490bbe6b5aSMichael van der Westhuizen .cpsr_val = SVC_MODE,
2500bbe6b5aSMichael van der Westhuizen .fn = tcm_handler
2510bbe6b5aSMichael van der Westhuizen };
2520bbe6b5aSMichael van der Westhuizen
2530bbe6b5aSMichael van der Westhuizen /*
254bc581770SLinus Walleij * This initializes the TCM memory
255bc581770SLinus Walleij */
tcm_init(void)256bc581770SLinus Walleij void __init tcm_init(void)
257bc581770SLinus Walleij {
25890b9222eSLinus Walleij u32 tcm_status;
25990b9222eSLinus Walleij u8 dtcm_banks;
26090b9222eSLinus Walleij u8 itcm_banks;
2619715efb8SLinus Walleij size_t dtcm_code_sz = &__edtcm_data - &__sdtcm_data;
2629715efb8SLinus Walleij size_t itcm_code_sz = &__eitcm_text - &__sitcm_text;
263bc581770SLinus Walleij char *start;
264bc581770SLinus Walleij char *end;
265bc581770SLinus Walleij char *ram;
2661dbd30e9SLinus Walleij int ret;
26759850977SLinus Walleij int i;
268bc581770SLinus Walleij
26990b9222eSLinus Walleij /*
27090b9222eSLinus Walleij * Prior to ARMv5 there is no TCM, and trying to read the status
27190b9222eSLinus Walleij * register will hang the processor.
27290b9222eSLinus Walleij */
27390b9222eSLinus Walleij if (cpu_architecture() < CPU_ARCH_ARMv5) {
27490b9222eSLinus Walleij if (dtcm_code_sz || itcm_code_sz)
27590b9222eSLinus Walleij pr_info("CPU TCM: %u bytes of DTCM and %u bytes of "
27690b9222eSLinus Walleij "ITCM code compiled in, but no TCM present "
27790b9222eSLinus Walleij "in pre-v5 CPU\n", dtcm_code_sz, itcm_code_sz);
27890b9222eSLinus Walleij return;
27990b9222eSLinus Walleij }
28090b9222eSLinus Walleij
28190b9222eSLinus Walleij tcm_status = read_cpuid_tcmstatus();
2820bbe6b5aSMichael van der Westhuizen
2830bbe6b5aSMichael van der Westhuizen /*
2840bbe6b5aSMichael van der Westhuizen * This code only supports v6-compatible TCMTR implementations.
2850bbe6b5aSMichael van der Westhuizen */
2860bbe6b5aSMichael van der Westhuizen if (tcm_status & TCMTR_FORMAT_MASK)
2870bbe6b5aSMichael van der Westhuizen return;
2880bbe6b5aSMichael van der Westhuizen
28990b9222eSLinus Walleij dtcm_banks = (tcm_status >> 16) & 0x03;
29090b9222eSLinus Walleij itcm_banks = (tcm_status & 0x03);
29190b9222eSLinus Walleij
2920bbe6b5aSMichael van der Westhuizen register_undef_hook(&tcm_hook);
2930bbe6b5aSMichael van der Westhuizen
2949715efb8SLinus Walleij /* Values greater than 2 for D/ITCM banks are "reserved" */
2959715efb8SLinus Walleij if (dtcm_banks > 2)
2969715efb8SLinus Walleij dtcm_banks = 0;
2979715efb8SLinus Walleij if (itcm_banks > 2)
2989715efb8SLinus Walleij itcm_banks = 0;
2999715efb8SLinus Walleij
300bc581770SLinus Walleij /* Setup DTCM if present */
3011dbd30e9SLinus Walleij if (dtcm_banks > 0) {
30259850977SLinus Walleij for (i = 0; i < dtcm_banks; i++) {
3031dbd30e9SLinus Walleij ret = setup_tcm_bank(0, i, dtcm_banks, &dtcm_end);
3041dbd30e9SLinus Walleij if (ret)
3050bbe6b5aSMichael van der Westhuizen goto unregister;
3061dbd30e9SLinus Walleij }
3079715efb8SLinus Walleij /* This means you compiled more code than fits into DTCM */
3089715efb8SLinus Walleij if (dtcm_code_sz > (dtcm_end - DTCM_OFFSET)) {
3099715efb8SLinus Walleij pr_info("CPU DTCM: %u bytes of code compiled to "
3109715efb8SLinus Walleij "DTCM but only %lu bytes of DTCM present\n",
3119715efb8SLinus Walleij dtcm_code_sz, (dtcm_end - DTCM_OFFSET));
3129715efb8SLinus Walleij goto no_dtcm;
3139715efb8SLinus Walleij }
3140bbe6b5aSMichael van der Westhuizen /*
3150bbe6b5aSMichael van der Westhuizen * This means that the DTCM sizes were 0 or the DTCM banks
3160bbe6b5aSMichael van der Westhuizen * were inaccessible due to TrustZone configuration.
3170bbe6b5aSMichael van der Westhuizen */
3180bbe6b5aSMichael van der Westhuizen if (!(dtcm_end - DTCM_OFFSET))
3190bbe6b5aSMichael van der Westhuizen goto no_dtcm;
3201dbd30e9SLinus Walleij dtcm_res.end = dtcm_end - 1;
321bc581770SLinus Walleij request_resource(&iomem_resource, &dtcm_res);
3221dbd30e9SLinus Walleij dtcm_iomap[0].length = dtcm_end - DTCM_OFFSET;
323bc581770SLinus Walleij iotable_init(dtcm_iomap, 1);
324bc581770SLinus Walleij /* Copy data from RAM to DTCM */
325bc581770SLinus Walleij start = &__sdtcm_data;
326bc581770SLinus Walleij end = &__edtcm_data;
327bc581770SLinus Walleij ram = &__dtcm_start;
3289715efb8SLinus Walleij memcpy(start, ram, dtcm_code_sz);
3299715efb8SLinus Walleij pr_debug("CPU DTCM: copied data from %p - %p\n",
3309715efb8SLinus Walleij start, end);
331201043f2SLinus Walleij dtcm_present = true;
3329715efb8SLinus Walleij } else if (dtcm_code_sz) {
3339715efb8SLinus Walleij pr_info("CPU DTCM: %u bytes of code compiled to DTCM but no "
3349715efb8SLinus Walleij "DTCM banks present in CPU\n", dtcm_code_sz);
335bc581770SLinus Walleij }
336bc581770SLinus Walleij
3379715efb8SLinus Walleij no_dtcm:
338bc581770SLinus Walleij /* Setup ITCM if present */
3391dbd30e9SLinus Walleij if (itcm_banks > 0) {
34059850977SLinus Walleij for (i = 0; i < itcm_banks; i++) {
3411dbd30e9SLinus Walleij ret = setup_tcm_bank(1, i, itcm_banks, &itcm_end);
3421dbd30e9SLinus Walleij if (ret)
3430bbe6b5aSMichael van der Westhuizen goto unregister;
3441dbd30e9SLinus Walleij }
3459715efb8SLinus Walleij /* This means you compiled more code than fits into ITCM */
3469715efb8SLinus Walleij if (itcm_code_sz > (itcm_end - ITCM_OFFSET)) {
3479715efb8SLinus Walleij pr_info("CPU ITCM: %u bytes of code compiled to "
3489715efb8SLinus Walleij "ITCM but only %lu bytes of ITCM present\n",
3499715efb8SLinus Walleij itcm_code_sz, (itcm_end - ITCM_OFFSET));
3500bbe6b5aSMichael van der Westhuizen goto unregister;
3519715efb8SLinus Walleij }
3520bbe6b5aSMichael van der Westhuizen /*
3530bbe6b5aSMichael van der Westhuizen * This means that the ITCM sizes were 0 or the ITCM banks
3540bbe6b5aSMichael van der Westhuizen * were inaccessible due to TrustZone configuration.
3550bbe6b5aSMichael van der Westhuizen */
3560bbe6b5aSMichael van der Westhuizen if (!(itcm_end - ITCM_OFFSET))
3570bbe6b5aSMichael van der Westhuizen goto unregister;
3581dbd30e9SLinus Walleij itcm_res.end = itcm_end - 1;
359bc581770SLinus Walleij request_resource(&iomem_resource, &itcm_res);
3601dbd30e9SLinus Walleij itcm_iomap[0].length = itcm_end - ITCM_OFFSET;
361bc581770SLinus Walleij iotable_init(itcm_iomap, 1);
362bc581770SLinus Walleij /* Copy code from RAM to ITCM */
363bc581770SLinus Walleij start = &__sitcm_text;
364bc581770SLinus Walleij end = &__eitcm_text;
365bc581770SLinus Walleij ram = &__itcm_start;
3669715efb8SLinus Walleij memcpy(start, ram, itcm_code_sz);
3679715efb8SLinus Walleij pr_debug("CPU ITCM: copied code from %p - %p\n",
3689715efb8SLinus Walleij start, end);
369201043f2SLinus Walleij itcm_present = true;
3709715efb8SLinus Walleij } else if (itcm_code_sz) {
3719715efb8SLinus Walleij pr_info("CPU ITCM: %u bytes of code compiled to ITCM but no "
3729715efb8SLinus Walleij "ITCM banks present in CPU\n", itcm_code_sz);
373bc581770SLinus Walleij }
3740bbe6b5aSMichael van der Westhuizen
3750bbe6b5aSMichael van der Westhuizen unregister:
3760bbe6b5aSMichael van der Westhuizen unregister_undef_hook(&tcm_hook);
377bc581770SLinus Walleij }
378bc581770SLinus Walleij
379bc581770SLinus Walleij /*
380bc581770SLinus Walleij * This creates the TCM memory pool and has to be done later,
381bc581770SLinus Walleij * during the core_initicalls, since the allocator is not yet
382bc581770SLinus Walleij * up and running when the first initialization runs.
383bc581770SLinus Walleij */
setup_tcm_pool(void)384bc581770SLinus Walleij static int __init setup_tcm_pool(void)
385bc581770SLinus Walleij {
386bc581770SLinus Walleij u32 dtcm_pool_start = (u32) &__edtcm_data;
387bc581770SLinus Walleij u32 itcm_pool_start = (u32) &__eitcm_text;
388bc581770SLinus Walleij int ret;
389bc581770SLinus Walleij
390bc581770SLinus Walleij /*
391bc581770SLinus Walleij * Set up malloc pool, 2^2 = 4 bytes granularity since
392bc581770SLinus Walleij * the TCM is sometimes just 4 KiB. NB: pages and cache
393bc581770SLinus Walleij * line alignments does not matter in TCM!
394bc581770SLinus Walleij */
395bc581770SLinus Walleij tcm_pool = gen_pool_create(2, -1);
396bc581770SLinus Walleij
397bc581770SLinus Walleij pr_debug("Setting up TCM memory pool\n");
398bc581770SLinus Walleij
399bc581770SLinus Walleij /* Add the rest of DTCM to the TCM pool */
400201043f2SLinus Walleij if (dtcm_present) {
4011dbd30e9SLinus Walleij if (dtcm_pool_start < dtcm_end) {
402bc581770SLinus Walleij ret = gen_pool_add(tcm_pool, dtcm_pool_start,
4031dbd30e9SLinus Walleij dtcm_end - dtcm_pool_start, -1);
404bc581770SLinus Walleij if (ret) {
405bc581770SLinus Walleij pr_err("CPU DTCM: could not add DTCM " \
406bc581770SLinus Walleij "remainder to pool!\n");
407bc581770SLinus Walleij return ret;
408bc581770SLinus Walleij }
409bc581770SLinus Walleij pr_debug("CPU DTCM: Added %08x bytes @ %08x to " \
410bc581770SLinus Walleij "the TCM memory pool\n",
4111dbd30e9SLinus Walleij dtcm_end - dtcm_pool_start,
412bc581770SLinus Walleij dtcm_pool_start);
413bc581770SLinus Walleij }
414bc581770SLinus Walleij }
415bc581770SLinus Walleij
416bc581770SLinus Walleij /* Add the rest of ITCM to the TCM pool */
417201043f2SLinus Walleij if (itcm_present) {
4181dbd30e9SLinus Walleij if (itcm_pool_start < itcm_end) {
419bc581770SLinus Walleij ret = gen_pool_add(tcm_pool, itcm_pool_start,
4201dbd30e9SLinus Walleij itcm_end - itcm_pool_start, -1);
421bc581770SLinus Walleij if (ret) {
422bc581770SLinus Walleij pr_err("CPU ITCM: could not add ITCM " \
423bc581770SLinus Walleij "remainder to pool!\n");
424bc581770SLinus Walleij return ret;
425bc581770SLinus Walleij }
426bc581770SLinus Walleij pr_debug("CPU ITCM: Added %08x bytes @ %08x to " \
427bc581770SLinus Walleij "the TCM memory pool\n",
4281dbd30e9SLinus Walleij itcm_end - itcm_pool_start,
429bc581770SLinus Walleij itcm_pool_start);
430bc581770SLinus Walleij }
431bc581770SLinus Walleij }
432bc581770SLinus Walleij return 0;
433bc581770SLinus Walleij }
434bc581770SLinus Walleij
435bc581770SLinus Walleij core_initcall(setup_tcm_pool);
436