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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dnvidia,tegra20-emc.txt4 - name : Should be emc
5 - #address-cells : Should be 1
6 - #size-cells : Should be 0
7 - compatible : Should contain "nvidia,tegra20-emc".
8 - reg : Offset and length of the register set for the device
9 - nvidia,use-ram-code : If present, the sub-nodes will be addressed
12 irrespective of ram-code configuration.
13 - interrupts : Should contain EMC General interrupt.
14 - clocks : Should contain EMC clock.
15 - nvidia,memory-controller : Phandle of the Memory Controller node.
[all …]
H A Dnvidia,tegra20-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
17 various performance-affecting settings beyond the obvious SDRAM configuration
23 const: nvidia,tegra20-emc
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H A Dnvidia,tegra124-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
22 const: nvidia,tegra124-mc
30 clock-names:
32 - const: mc
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H A Dnvidia,tegra30-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
39 const: nvidia,tegra30-mc
47 clock-names:
49 - const: mc
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/freebsd/sys/dev/ixl/
H A Di40e_nvm.c3 Copyright (c) 2013-2018, Intel Corporation
9 1. Redistributions of source code must retain the above copyright notice,
37 * i40e_init_nvm - Initialize NVM function pointers
44 * We are accessing FLASH always through the Shadow RAM.
48 struct i40e_nvm_info *nvm = &hw->nvm; in i40e_init_nvm()
62 nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB; in i40e_init_nvm()
68 nvm->timeout = I40E_MAX_NVM_TIMEOUT; in i40e_init_nvm()
69 nvm->blank_nvm_mode = FALSE; in i40e_init_nvm()
71 nvm->blank_nvm_mode = TRUE; in i40e_init_nvm()
80 * i40e_acquire_nvm - Generic request for acquiring the NVM ownership
[all …]
/freebsd/usr.sbin/bhyve/amd64/
H A De820.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
25 * E820 always uses 64 bit entries. Emulation code will use vm_paddr_t since it
67 element->base = base; in e820_element_alloc()
68 element->end = end; in e820_element_alloc()
69 element->type = type; in e820_element_alloc()
79 return ("RAM"); in e820_get_type_name()
102 element->base, element->end, in e820_dump_table()
103 e820_get_type_name(element->type)); in e820_dump_table()
131 fwcfg_item->size = count * sizeof(struct e820_entry); in e820_get_fwcfg_item()
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H A Datkbdc.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
11 * 1. Redistributions of source code must retain the above copyright
129 uint8_t ram[RAMSZ]; /* byte0 = controller config */ member
145 if ((sc->ram[0] & KBD_ENABLE_KBD_INT) != 0) { in atkbdc_assert_kbd_intr()
146 sc->kbd.irq_active = true; in atkbdc_assert_kbd_intr()
147 vm_isa_pulse_irq(sc->ctx, sc->kbd.irq, sc->kbd.irq); in atkbdc_assert_kbd_intr()
154 if ((sc->ram[0] & KBD_ENABLE_AUX_INT) != 0) { in atkbdc_assert_aux_intr()
155 sc->aux.irq_active = true; in atkbdc_assert_aux_intr()
156 vm_isa_pulse_irq(sc->ctx, sc->aux.irq, sc->aux.irq); in atkbdc_assert_aux_intr()
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/freebsd/sys/sys/
H A Dphysmem.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
10 * 1. Redistributions of source code must retain the above copyright
37 * Routines to help configure physical ram.
39 * Multiple regions of contiguous physical ram can be added (in any order).
41 * Multiple regions of physical ram that should be excluded from crash dumps, or
45 * remainining non-excluded physical ram for use by other parts of the kernel,
48 * that communicate physical ram configuration to other parts of the kernel.
72 while (mrcount--) { in physmem_hardware_regions()
73 physmem_hardware_region(mrptr->mr_start, mrptr->mr_size); in physmem_hardware_regions()
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/freebsd/usr.sbin/makefs/cd9660/
H A Dcd9660_strings.c3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
7 * Perez-Rathke and Ram Vedam. All rights reserved.
9 * This code was written by Daniel Watt, Walter Deignan, Ryan Gabrys,
10 * Alan Perez-Rathke and Ram Vedam.
15 * 1. Redistributions of source code must retain the above copyright
23 * GABRYS, ALAN PEREZ-RATHKE AND RAM VEDAM ``AS IS'' AND ANY EXPRESS OR
27 * GABRYS, ALAN PEREZ-RATHKE AND RAM VEDAM BE LIABLE FOR ANY DIRECT, INDIRECT,
53 str[p] -= 32; in cd9660_uppercase_characters()
H A Dcd9660_conversion.c3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
7 * Perez-Rathke and Ram Vedam. All rights reserved.
9 * This code was written by Daniel Watt, Walter Deignan, Ryan Gabrys,
10 * Alan Perez-Rathke and Ram Vedam.
15 * 1. Redistributions of source code must retain the above copyright
23 * GABRYS, ALAN PEREZ-RATHKE AND RAM VEDAM ``AS IS'' AND ANY EXPRESS OR
27 * GABRYS, ALAN PEREZ-RATHKE AND RAM VEDAM BE LIABLE FOR ANY DIRECT, INDIRECT,
95 * @param char* The string to write the both endian double word to - It is assumed this is allocated…
117 * @param char* The string to write the both endian word to - It is assumed this is allocated and at…
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H A Dcd9660_eltorito.h3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
7 * Perez-Rathke and Ram Vedam. All rights reserved.
9 * This code was written by Daniel Watt, Walter Deignan, Ryan Gabrys,
10 * Alan Perez-Rathke and Ram Vedam.
15 * 1. Redistributions of source code must retain the above copyright
23 * GABRYS, ALAN PEREZ-RATHKE AND RAM VEDAM ``AS IS'' AND ANY EXPRESS OR
27 * GABRYS, ALAN PEREZ-RATHKE AND RAM VEDAM BE LIABLE FOR ANY DIRECT, INDIRECT,
H A Diso9660_rrip.h3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
7 * Perez-Rathke and Ram Vedam. All rights reserved.
9 * This code was written by Daniel Watt, Walter Deignan, Ryan Gabrys,
10 * Alan Perez-Rathke and Ram Vedam.
15 * 1. Redistributions of source code must retain the above copyright
23 * GABRYS, ALAN PEREZ-RATHKE AND RAM VEDAM ``AS IS'' AND ANY EXPRESS OR
27 * GABRYS, ALAN PEREZ-RATHKE AND RAM VEDAM BE LIABLE FOR ANY DIRECT, INDIRECT,
209 /* Dan's addons - will merge later. This allows use of a switch */
217 ((int) ((entry)->attr.su_entry.SP.h.length[0]))
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/freebsd/sys/arm64/coresight/
H A Dcoresight_tmc.h1 /*-
2 * Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com>
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
12 * 1. Redistributions of source code must retain the above copyright
34 #define TMC_RSZ 0x004 /* RAM Size Register */
42 #define TMC_RRD 0x010 /* RAM Read Data Register */
43 #define TMC_RRP 0x014 /* RAM Read Pointer Register */
44 #define TMC_RWP 0x018 /* RAM Write Pointer Register */
48 #define TMC_RWD 0x024 /* RAM Write Data Register */
56 #define TMC_RRPHI 0x038 /* RAM Read Pointer High Register */
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/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Dnvidia,tegra20-apbmisc.txt4 - compatible: Must be:
5 - Tegra20: "nvidia,tegra20-apbmisc"
6 - Tegra30: "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"
7 - Tegra114: "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"
8 - Tegra124: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"
9 - Tegra132: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"
10 - Tegra210: "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"
11 - reg: Should contain 2 entries: the first entry gives the physical address
17 - nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit).
H A Dnvidia,tegra20-apbmisc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/nvidia,tegra20-apbmisc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - items:
17 - enum:
18 - nvidia,tegra210-apbmisc
19 - nvidia,tegra124-apbmisc
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/freebsd/sys/dev/isci/scil/
H A Dscic_controller.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
35 * * Redistributions of source code must retain the above copyright
225 * number of MSI-X messages to be utilized. This parameter must
232 * - size = sizeof(SCIC_CONTROLLER_HANDLER_METHODS_T)
234 * - size = message_count*sizeof(SCIC_CONTROLLER_HANDLER_METHODS_T)
244 * array is zero-relative where entry zero corresponds to
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dnvidia,tegra124-car.txt4 Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
17 <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
18 to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
19 (for Tegra124-specific clocks).
20 - #reset-cells : Should be 1.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dfsl,xcvr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd/sys/dev/ice/
H A Dice_nvm.c1 /* SPDX-License-Identifier: BSD-3-Clause */
8 * 1. Redistributions of source code must retain the above copyright notice,
44 * @read_shadow_ram: tell if this is a shadow RAM read
67 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY; in ice_aq_read_nvm()
71 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD; in ice_aq_read_nvm()
72 cmd->module_typeid = CPU_TO_LE16(module_typeid); in ice_aq_read_nvm()
73 cmd->offset_lo in ice_aq_read_nvm()
[all...]
/freebsd/sys/arm/altera/socfpga/
H A Dsocfpga_mp.c1 /*-
2 * Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com>
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
12 * 1. Redistributions of source code must retain the above copyright
110 mp_maxid = ncpu - 1; in socfpga_mp_setmaxid()
116 bus_space_handle_t scu, rst, ram; in _socfpga_mp_start_ap() local
142 RAM_SIZE, 0, &ram) != 0) in _socfpga_mp_start_ap()
151 * Setting the "disable-migratory bit" in the undocumented SCU in _socfpga_mp_start_ap()
181 /* Set up trampoline code */ in _socfpga_mp_start_ap()
183 bus_space_write_region_4(fdtbus_bs_tag, ram, 0, in _socfpga_mp_start_ap()
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/freebsd/sys/dev/e1000/
H A De1000_i210.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
10 1. Redistributions of source code must retain the above copyright notice,
46 * e1000_acquire_nvm_i210 - Request for access to EEPROM
52 * EEPROM access and return -E1000_ERR_NVM (-1).
66 * e1000_release_nvm_i210 - Release exclusive access to EEPROM
80 * e1000_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register
82 * @offset: offset of word in the Shadow Ram to read
84 * @data: word read from the Shadow Ram
86 * Reads a 16 bit word from the Shadow Ram using the EERD register.
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/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Dkirkwood-ts219-6282.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "kirkwood-6282.dtsi"
6 #include "kirkwood-ts219.dtsi"
10 pinctrl: pin-controller@10000 {
12 pinctrl-0 = <&pmx_ram_size &pmx_board_id>;
13 pinctrl-names = "default";
15 pmx_ram_size: pmx-ram-size {
16 /* RAM: 0: 256 MB, 1: 512 MB */
20 pmx_reset_button: pmx-reset-button {
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H A Dkirkwood-ts219-6281.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "kirkwood-6281.dtsi"
6 #include "kirkwood-ts219.dtsi"
10 pinctrl: pin-controller@10000 {
12 pinctrl-0 = <&pmx_ram_size &pmx_board_id>;
13 pinctrl-names = "default";
15 pmx_ram_size: pmx-ram-size {
16 /* RAM: 0: 256 MB, 1: 512 MB */
20 pmx_USB_copy_button: pmx-USB-copy-button {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dmtd-physmap.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
10 - Rob Herring <robh@kernel.org>
17 - $ref: mtd.yaml#
18 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
23 - items:
24 - enum:
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/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/cpm/
H A Di2c.txt6 - compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c"
7 - reg : On CPM2 devices, the second resource doesn't specify the I2C
8 Parameter RAM itself, but the I2C_BASE field of the CPM2 Parameter RAM
10 - #address-cells : Should be one. The cell is the i2c device address with
12 - #size-cells : Should be zero.
13 - clock-frequency : Can be used to set the i2c clock frequency. If
17 - linux,i2c-index : Can be used to hard code an i2c bus number. By default,
19 - linux,i2c-class : Can be used to override the i2c class. The class is used
28 compatible = "fsl,mpc823-i2c",
29 "fsl,cpm1-i2c";
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